1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __DDR_H__ 8 #define __DDR_H__ 9 struct board_specific_parameters { 10 u32 n_ranks; 11 u32 datarate_mhz_high; 12 u32 rank_gb; 13 u32 clk_adjust; 14 u32 wrlvl_start; 15 u32 wrlvl_ctl_2; 16 u32 wrlvl_ctl_3; 17 }; 18 19 /* 20 * These tables contain all valid speeds we want to override with board 21 * specific parameters. datarate_mhz_high values need to be in ascending order 22 * for each n_ranks group. 23 */ 24 25 static const struct board_specific_parameters udimm0[] = { 26 /* 27 * memory controller 0 28 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 29 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 30 */ 31 {2, 2140, 0, 4, 4, 0x0, 0x0}, 32 {1, 2140, 0, 4, 4, 0x0, 0x0}, 33 {} 34 }; 35 36 /* DP-DDR DIMM */ 37 static const struct board_specific_parameters udimm2[] = { 38 /* 39 * memory controller 2 40 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 41 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 42 */ 43 {2, 2140, 0, 4, 4, 0x0, 0x0}, 44 {1, 2140, 0, 4, 4, 0x0, 0x0}, 45 {} 46 }; 47 48 static const struct board_specific_parameters rdimm0[] = { 49 /* 50 * memory controller 0 51 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 52 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 53 */ 54 {4, 2140, 0, 5, 4, 0x0, 0x0}, 55 {2, 2140, 0, 5, 4, 0x0, 0x0}, 56 {1, 2140, 0, 4, 4, 0x0, 0x0}, 57 {} 58 }; 59 60 /* DP-DDR DIMM */ 61 static const struct board_specific_parameters rdimm2[] = { 62 /* 63 * memory controller 2 64 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl 65 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 66 */ 67 {4, 2140, 0, 5, 4, 0x0, 0x0}, 68 {2, 2140, 0, 5, 4, 0x0, 0x0}, 69 {1, 2140, 0, 4, 4, 0x0, 0x0}, 70 {} 71 }; 72 73 static const struct board_specific_parameters *udimms[] = { 74 udimm0, 75 udimm0, 76 udimm2, 77 }; 78 79 static const struct board_specific_parameters *rdimms[] = { 80 rdimm0, 81 rdimm0, 82 rdimm2, 83 }; 84 85 86 #endif 87