1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fsl_ddr_sdram.h> 9 #include <fsl_ddr_dimm_params.h> 10 #include "ddr.h" 11 12 DECLARE_GLOBAL_DATA_PTR; 13 14 void fsl_ddr_board_options(memctl_options_t *popts, 15 dimm_params_t *pdimm, 16 unsigned int ctrl_num) 17 { 18 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 19 ulong ddr_freq; 20 21 if (ctrl_num > 3) { 22 printf("Not supported controller number %d\n", ctrl_num); 23 return; 24 } 25 if (!pdimm->n_ranks) 26 return; 27 28 /* 29 * we use identical timing for all slots. If needed, change the code 30 * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; 31 */ 32 if (popts->registered_dimm_en) 33 pbsp = rdimms[ctrl_num]; 34 else 35 pbsp = udimms[ctrl_num]; 36 37 38 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr 39 * freqency and n_banks specified in board_specific_parameters table. 40 */ 41 ddr_freq = get_ddr_freq(0) / 1000000; 42 while (pbsp->datarate_mhz_high) { 43 if (pbsp->n_ranks == pdimm->n_ranks && 44 (pdimm->rank_density >> 30) >= pbsp->rank_gb) { 45 if (ddr_freq <= pbsp->datarate_mhz_high) { 46 popts->clk_adjust = pbsp->clk_adjust; 47 popts->wrlvl_start = pbsp->wrlvl_start; 48 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 49 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 50 goto found; 51 } 52 pbsp_highest = pbsp; 53 } 54 pbsp++; 55 } 56 57 if (pbsp_highest) { 58 printf("Error: board specific timing not found for data rate %lu MT/s\n" 59 "Trying to use the highest speed (%u) parameters\n", 60 ddr_freq, pbsp_highest->datarate_mhz_high); 61 popts->clk_adjust = pbsp_highest->clk_adjust; 62 popts->wrlvl_start = pbsp_highest->wrlvl_start; 63 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 64 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 65 } else { 66 panic("DIMM is not supported by this board"); 67 } 68 found: 69 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" 70 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", 71 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, 72 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, 73 pbsp->wrlvl_ctl_3); 74 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 75 if (ctrl_num == CONFIG_DP_DDR_CTRL) { 76 /* force DDR bus width to 32 bits */ 77 popts->data_bus_width = 1; 78 popts->otf_burst_chop_en = 0; 79 popts->burst_length = DDR_BL8; 80 popts->bstopre = 0; /* enable auto precharge */ 81 } 82 #endif 83 /* 84 * Factors to consider for half-strength driver enable: 85 * - number of DIMMs installed 86 */ 87 popts->half_strength_driver_enable = 1; 88 /* 89 * Write leveling override 90 */ 91 popts->wrlvl_override = 1; 92 popts->wrlvl_sample = 0xf; 93 94 /* 95 * Rtt and Rtt_WR override 96 */ 97 popts->rtt_override = 0; 98 99 /* Enable ZQ calibration */ 100 popts->zq_en = 1; 101 102 #ifdef CONFIG_SYS_FSL_DDR4 103 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); 104 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | 105 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ 106 #else 107 /* DHC_EN =1, ODT = 75 Ohm */ 108 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); 109 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); 110 #endif 111 } 112 113 #ifdef CONFIG_SYS_DDR_RAW_TIMING 114 dimm_params_t ddr_raw_timing = { 115 .n_ranks = 2, 116 .rank_density = 1073741824u, 117 .capacity = 2147483648, 118 .primary_sdram_width = 64, 119 .ec_sdram_width = 0, 120 .registered_dimm = 0, 121 .mirrored_dimm = 0, 122 .n_row_addr = 14, 123 .n_col_addr = 10, 124 .n_banks_per_sdram_device = 8, 125 .edc_config = 0, 126 .burst_lengths_bitmask = 0x0c, 127 128 .tckmin_x_ps = 937, 129 .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */ 130 .taa_ps = 13090, 131 .twr_ps = 15000, 132 .trcd_ps = 13090, 133 .trrd_ps = 5000, 134 .trp_ps = 13090, 135 .tras_ps = 33000, 136 .trc_ps = 46090, 137 .trfc_ps = 160000, 138 .twtr_ps = 7500, 139 .trtp_ps = 7500, 140 .refresh_rate_ps = 7800000, 141 .tfaw_ps = 25000, 142 }; 143 144 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 145 unsigned int controller_number, 146 unsigned int dimm_number) 147 { 148 const char dimm_model[] = "Fixed DDR on board"; 149 150 if (((controller_number == 0) && (dimm_number == 0)) || 151 ((controller_number == 1) && (dimm_number == 0))) { 152 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 153 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 154 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 155 } 156 157 return 0; 158 } 159 #endif 160 phys_size_t initdram(int board_type) 161 { 162 phys_size_t dram_size; 163 164 puts("Initializing DDR...."); 165 166 puts("using SPD\n"); 167 dram_size = fsl_ddr_sdram(); 168 169 return dram_size; 170 } 171 172 void dram_init_banksize(void) 173 { 174 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY 175 phys_size_t dp_ddr_size; 176 #endif 177 178 /* 179 * gd->secure_ram tracks the location of secure memory. 180 * It was set as if the memory starts from 0. 181 * The address needs to add the offset of its bank. 182 */ 183 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 184 if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { 185 gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; 186 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; 187 gd->bd->bi_dram[1].size = gd->ram_size - 188 CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; 189 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 190 gd->secure_ram = gd->bd->bi_dram[1].start + 191 gd->secure_ram - 192 CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; 193 gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; 194 #endif 195 } else { 196 gd->bd->bi_dram[0].size = gd->ram_size; 197 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 198 gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; 199 gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; 200 #endif 201 } 202 203 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY 204 /* initialize DP-DDR here */ 205 puts("DP-DDR: "); 206 /* 207 * DDR controller use 0 as the base address for binding. 208 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 209 */ 210 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, 211 CONFIG_DP_DDR_CTRL, 212 CONFIG_DP_DDR_NUM_CTRLS, 213 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, 214 NULL, NULL, NULL); 215 if (dp_ddr_size) { 216 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; 217 gd->bd->bi_dram[2].size = dp_ddr_size; 218 } else { 219 puts("Not detected"); 220 } 221 #endif 222 } 223