1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fsl_ddr_sdram.h> 9 #include <fsl_ddr_dimm_params.h> 10 #include <asm/arch/soc.h> 11 #include <asm/arch/clock.h> 12 #include "ddr.h" 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 void fsl_ddr_board_options(memctl_options_t *popts, 17 dimm_params_t *pdimm, 18 unsigned int ctrl_num) 19 { 20 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 21 ulong ddr_freq; 22 23 if (ctrl_num > 3) { 24 printf("Not supported controller number %d\n", ctrl_num); 25 return; 26 } 27 if (!pdimm->n_ranks) 28 return; 29 30 /* 31 * we use identical timing for all slots. If needed, change the code 32 * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; 33 */ 34 if (popts->registered_dimm_en) 35 pbsp = rdimms[ctrl_num]; 36 else 37 pbsp = udimms[ctrl_num]; 38 39 40 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr 41 * freqency and n_banks specified in board_specific_parameters table. 42 */ 43 ddr_freq = get_ddr_freq(0) / 1000000; 44 while (pbsp->datarate_mhz_high) { 45 if (pbsp->n_ranks == pdimm->n_ranks && 46 (pdimm->rank_density >> 30) >= pbsp->rank_gb) { 47 if (ddr_freq <= pbsp->datarate_mhz_high) { 48 popts->clk_adjust = pbsp->clk_adjust; 49 popts->wrlvl_start = pbsp->wrlvl_start; 50 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 51 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 52 goto found; 53 } 54 pbsp_highest = pbsp; 55 } 56 pbsp++; 57 } 58 59 if (pbsp_highest) { 60 printf("Error: board specific timing not found for data rate %lu MT/s\n" 61 "Trying to use the highest speed (%u) parameters\n", 62 ddr_freq, pbsp_highest->datarate_mhz_high); 63 popts->clk_adjust = pbsp_highest->clk_adjust; 64 popts->wrlvl_start = pbsp_highest->wrlvl_start; 65 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 66 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 67 } else { 68 panic("DIMM is not supported by this board"); 69 } 70 found: 71 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" 72 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", 73 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, 74 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, 75 pbsp->wrlvl_ctl_3); 76 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 77 if (ctrl_num == CONFIG_DP_DDR_CTRL) { 78 /* force DDR bus width to 32 bits */ 79 popts->data_bus_width = 1; 80 popts->otf_burst_chop_en = 0; 81 popts->burst_length = DDR_BL8; 82 popts->bstopre = 0; /* enable auto precharge */ 83 } 84 #endif 85 /* 86 * Factors to consider for half-strength driver enable: 87 * - number of DIMMs installed 88 */ 89 popts->half_strength_driver_enable = 1; 90 /* 91 * Write leveling override 92 */ 93 popts->wrlvl_override = 1; 94 popts->wrlvl_sample = 0xf; 95 96 /* 97 * Rtt and Rtt_WR override 98 */ 99 popts->rtt_override = 0; 100 101 /* Enable ZQ calibration */ 102 popts->zq_en = 1; 103 104 #ifdef CONFIG_SYS_FSL_DDR4 105 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); 106 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | 107 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ 108 #else 109 /* DHC_EN =1, ODT = 75 Ohm */ 110 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); 111 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); 112 #endif 113 } 114 115 #ifdef CONFIG_SYS_DDR_RAW_TIMING 116 dimm_params_t ddr_raw_timing = { 117 .n_ranks = 2, 118 .rank_density = 1073741824u, 119 .capacity = 2147483648, 120 .primary_sdram_width = 64, 121 .ec_sdram_width = 0, 122 .registered_dimm = 0, 123 .mirrored_dimm = 0, 124 .n_row_addr = 14, 125 .n_col_addr = 10, 126 .n_banks_per_sdram_device = 8, 127 .edc_config = 0, 128 .burst_lengths_bitmask = 0x0c, 129 130 .tckmin_x_ps = 937, 131 .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */ 132 .taa_ps = 13090, 133 .twr_ps = 15000, 134 .trcd_ps = 13090, 135 .trrd_ps = 5000, 136 .trp_ps = 13090, 137 .tras_ps = 33000, 138 .trc_ps = 46090, 139 .trfc_ps = 160000, 140 .twtr_ps = 7500, 141 .trtp_ps = 7500, 142 .refresh_rate_ps = 7800000, 143 .tfaw_ps = 25000, 144 }; 145 146 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 147 unsigned int controller_number, 148 unsigned int dimm_number) 149 { 150 const char dimm_model[] = "Fixed DDR on board"; 151 152 if (((controller_number == 0) && (dimm_number == 0)) || 153 ((controller_number == 1) && (dimm_number == 0))) { 154 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 155 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 156 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 157 } 158 159 return 0; 160 } 161 #endif 162 163 int fsl_initdram(void) 164 { 165 puts("Initializing DDR...."); 166 167 puts("using SPD\n"); 168 gd->ram_size = fsl_ddr_sdram(); 169 170 return 0; 171 } 172