1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 244937214SPrabhakar Kushwaha /* 344937214SPrabhakar Kushwaha * Copyright 2014 Freescale Semiconductor, Inc. 444937214SPrabhakar Kushwaha */ 544937214SPrabhakar Kushwaha 644937214SPrabhakar Kushwaha #include <common.h> 744937214SPrabhakar Kushwaha #include <fsl_ddr_sdram.h> 844937214SPrabhakar Kushwaha #include <fsl_ddr_dimm_params.h> 93c1d218aSYork Sun #include <asm/arch/soc.h> 106e2941d7SSimon Glass #include <asm/arch/clock.h> 1144937214SPrabhakar Kushwaha #include "ddr.h" 1244937214SPrabhakar Kushwaha 1344937214SPrabhakar Kushwaha DECLARE_GLOBAL_DATA_PTR; 1444937214SPrabhakar Kushwaha 1544937214SPrabhakar Kushwaha void fsl_ddr_board_options(memctl_options_t *popts, 1644937214SPrabhakar Kushwaha dimm_params_t *pdimm, 1744937214SPrabhakar Kushwaha unsigned int ctrl_num) 1844937214SPrabhakar Kushwaha { 1944937214SPrabhakar Kushwaha const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 2044937214SPrabhakar Kushwaha ulong ddr_freq; 2144937214SPrabhakar Kushwaha 2244937214SPrabhakar Kushwaha if (ctrl_num > 3) { 2344937214SPrabhakar Kushwaha printf("Not supported controller number %d\n", ctrl_num); 2444937214SPrabhakar Kushwaha return; 2544937214SPrabhakar Kushwaha } 2644937214SPrabhakar Kushwaha if (!pdimm->n_ranks) 2744937214SPrabhakar Kushwaha return; 2844937214SPrabhakar Kushwaha 2944937214SPrabhakar Kushwaha /* 3044937214SPrabhakar Kushwaha * we use identical timing for all slots. If needed, change the code 3144937214SPrabhakar Kushwaha * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; 3244937214SPrabhakar Kushwaha */ 3344937214SPrabhakar Kushwaha if (popts->registered_dimm_en) 3444937214SPrabhakar Kushwaha pbsp = rdimms[ctrl_num]; 3544937214SPrabhakar Kushwaha else 3644937214SPrabhakar Kushwaha pbsp = udimms[ctrl_num]; 3744937214SPrabhakar Kushwaha 3844937214SPrabhakar Kushwaha 3944937214SPrabhakar Kushwaha /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr 4044937214SPrabhakar Kushwaha * freqency and n_banks specified in board_specific_parameters table. 4144937214SPrabhakar Kushwaha */ 4244937214SPrabhakar Kushwaha ddr_freq = get_ddr_freq(0) / 1000000; 4344937214SPrabhakar Kushwaha while (pbsp->datarate_mhz_high) { 4444937214SPrabhakar Kushwaha if (pbsp->n_ranks == pdimm->n_ranks && 4544937214SPrabhakar Kushwaha (pdimm->rank_density >> 30) >= pbsp->rank_gb) { 4644937214SPrabhakar Kushwaha if (ddr_freq <= pbsp->datarate_mhz_high) { 4744937214SPrabhakar Kushwaha popts->clk_adjust = pbsp->clk_adjust; 4844937214SPrabhakar Kushwaha popts->wrlvl_start = pbsp->wrlvl_start; 4944937214SPrabhakar Kushwaha popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 5044937214SPrabhakar Kushwaha popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 5144937214SPrabhakar Kushwaha goto found; 5244937214SPrabhakar Kushwaha } 5344937214SPrabhakar Kushwaha pbsp_highest = pbsp; 5444937214SPrabhakar Kushwaha } 5544937214SPrabhakar Kushwaha pbsp++; 5644937214SPrabhakar Kushwaha } 5744937214SPrabhakar Kushwaha 5844937214SPrabhakar Kushwaha if (pbsp_highest) { 5944937214SPrabhakar Kushwaha printf("Error: board specific timing not found for data rate %lu MT/s\n" 6044937214SPrabhakar Kushwaha "Trying to use the highest speed (%u) parameters\n", 6144937214SPrabhakar Kushwaha ddr_freq, pbsp_highest->datarate_mhz_high); 6244937214SPrabhakar Kushwaha popts->clk_adjust = pbsp_highest->clk_adjust; 6344937214SPrabhakar Kushwaha popts->wrlvl_start = pbsp_highest->wrlvl_start; 6444937214SPrabhakar Kushwaha popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 6544937214SPrabhakar Kushwaha popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 6644937214SPrabhakar Kushwaha } else { 6744937214SPrabhakar Kushwaha panic("DIMM is not supported by this board"); 6844937214SPrabhakar Kushwaha } 6944937214SPrabhakar Kushwaha found: 7044937214SPrabhakar Kushwaha debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" 7144937214SPrabhakar Kushwaha "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", 7244937214SPrabhakar Kushwaha pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, 7344937214SPrabhakar Kushwaha pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, 7444937214SPrabhakar Kushwaha pbsp->wrlvl_ctl_3); 7544937214SPrabhakar Kushwaha #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 7644937214SPrabhakar Kushwaha if (ctrl_num == CONFIG_DP_DDR_CTRL) { 7744937214SPrabhakar Kushwaha /* force DDR bus width to 32 bits */ 7844937214SPrabhakar Kushwaha popts->data_bus_width = 1; 7944937214SPrabhakar Kushwaha popts->otf_burst_chop_en = 0; 8044937214SPrabhakar Kushwaha popts->burst_length = DDR_BL8; 8144937214SPrabhakar Kushwaha popts->bstopre = 0; /* enable auto precharge */ 8244937214SPrabhakar Kushwaha } 8344937214SPrabhakar Kushwaha #endif 8444937214SPrabhakar Kushwaha /* 8544937214SPrabhakar Kushwaha * Factors to consider for half-strength driver enable: 8644937214SPrabhakar Kushwaha * - number of DIMMs installed 8744937214SPrabhakar Kushwaha */ 8844937214SPrabhakar Kushwaha popts->half_strength_driver_enable = 1; 8944937214SPrabhakar Kushwaha /* 9044937214SPrabhakar Kushwaha * Write leveling override 9144937214SPrabhakar Kushwaha */ 9244937214SPrabhakar Kushwaha popts->wrlvl_override = 1; 9344937214SPrabhakar Kushwaha popts->wrlvl_sample = 0xf; 9444937214SPrabhakar Kushwaha 9544937214SPrabhakar Kushwaha /* 9644937214SPrabhakar Kushwaha * Rtt and Rtt_WR override 9744937214SPrabhakar Kushwaha */ 9844937214SPrabhakar Kushwaha popts->rtt_override = 0; 9944937214SPrabhakar Kushwaha 10044937214SPrabhakar Kushwaha /* Enable ZQ calibration */ 10144937214SPrabhakar Kushwaha popts->zq_en = 1; 10244937214SPrabhakar Kushwaha 10344937214SPrabhakar Kushwaha #ifdef CONFIG_SYS_FSL_DDR4 10444937214SPrabhakar Kushwaha popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); 10544937214SPrabhakar Kushwaha popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | 10644937214SPrabhakar Kushwaha DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ 10744937214SPrabhakar Kushwaha #else 10844937214SPrabhakar Kushwaha /* DHC_EN =1, ODT = 75 Ohm */ 10944937214SPrabhakar Kushwaha popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); 11044937214SPrabhakar Kushwaha popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); 11144937214SPrabhakar Kushwaha #endif 11244937214SPrabhakar Kushwaha } 11344937214SPrabhakar Kushwaha 11444937214SPrabhakar Kushwaha #ifdef CONFIG_SYS_DDR_RAW_TIMING 11544937214SPrabhakar Kushwaha dimm_params_t ddr_raw_timing = { 11644937214SPrabhakar Kushwaha .n_ranks = 2, 11744937214SPrabhakar Kushwaha .rank_density = 1073741824u, 11844937214SPrabhakar Kushwaha .capacity = 2147483648, 11944937214SPrabhakar Kushwaha .primary_sdram_width = 64, 12044937214SPrabhakar Kushwaha .ec_sdram_width = 0, 12144937214SPrabhakar Kushwaha .registered_dimm = 0, 12244937214SPrabhakar Kushwaha .mirrored_dimm = 0, 12344937214SPrabhakar Kushwaha .n_row_addr = 14, 12444937214SPrabhakar Kushwaha .n_col_addr = 10, 12544937214SPrabhakar Kushwaha .n_banks_per_sdram_device = 8, 12644937214SPrabhakar Kushwaha .edc_config = 0, 12744937214SPrabhakar Kushwaha .burst_lengths_bitmask = 0x0c, 12844937214SPrabhakar Kushwaha 12944937214SPrabhakar Kushwaha .tckmin_x_ps = 937, 13044937214SPrabhakar Kushwaha .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */ 13144937214SPrabhakar Kushwaha .taa_ps = 13090, 13244937214SPrabhakar Kushwaha .twr_ps = 15000, 13344937214SPrabhakar Kushwaha .trcd_ps = 13090, 13444937214SPrabhakar Kushwaha .trrd_ps = 5000, 13544937214SPrabhakar Kushwaha .trp_ps = 13090, 13644937214SPrabhakar Kushwaha .tras_ps = 33000, 13744937214SPrabhakar Kushwaha .trc_ps = 46090, 13844937214SPrabhakar Kushwaha .trfc_ps = 160000, 13944937214SPrabhakar Kushwaha .twtr_ps = 7500, 14044937214SPrabhakar Kushwaha .trtp_ps = 7500, 14144937214SPrabhakar Kushwaha .refresh_rate_ps = 7800000, 14244937214SPrabhakar Kushwaha .tfaw_ps = 25000, 14344937214SPrabhakar Kushwaha }; 14444937214SPrabhakar Kushwaha 14544937214SPrabhakar Kushwaha int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 14644937214SPrabhakar Kushwaha unsigned int controller_number, 14744937214SPrabhakar Kushwaha unsigned int dimm_number) 14844937214SPrabhakar Kushwaha { 14944937214SPrabhakar Kushwaha const char dimm_model[] = "Fixed DDR on board"; 15044937214SPrabhakar Kushwaha 15144937214SPrabhakar Kushwaha if (((controller_number == 0) && (dimm_number == 0)) || 15244937214SPrabhakar Kushwaha ((controller_number == 1) && (dimm_number == 0))) { 15344937214SPrabhakar Kushwaha memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 15444937214SPrabhakar Kushwaha memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 15544937214SPrabhakar Kushwaha memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 15644937214SPrabhakar Kushwaha } 15744937214SPrabhakar Kushwaha 15844937214SPrabhakar Kushwaha return 0; 15944937214SPrabhakar Kushwaha } 16044937214SPrabhakar Kushwaha #endif 1613eace37eSSimon Glass 1623eace37eSSimon Glass int fsl_initdram(void) 16344937214SPrabhakar Kushwaha { 16444937214SPrabhakar Kushwaha puts("Initializing DDR...."); 16544937214SPrabhakar Kushwaha 16644937214SPrabhakar Kushwaha puts("using SPD\n"); 167088454cdSSimon Glass gd->ram_size = fsl_ddr_sdram(); 16844937214SPrabhakar Kushwaha 169088454cdSSimon Glass return 0; 17044937214SPrabhakar Kushwaha } 171