1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2017 NXP
4  */
5 
6 #ifndef __LS1088AQDS_QIXIS_H__
7 #define __LS1088AQDS_QIXIS_H__
8 
9 /* Definitions of QIXIS Registers for LS1088AQDS */
10 
11 /* SYSCLK */
12 #define QIXIS_SYSCLK_66			0x0
13 #define QIXIS_SYSCLK_83			0x1
14 #define QIXIS_SYSCLK_100		0x2
15 #define QIXIS_SYSCLK_125		0x3
16 #define QIXIS_SYSCLK_133		0x4
17 #define QIXIS_SYSCLK_150		0x5
18 #define QIXIS_SYSCLK_160		0x6
19 #define QIXIS_SYSCLK_166		0x7
20 
21 /* DDRCLK */
22 #define QIXIS_DDRCLK_66			0x0
23 #define QIXIS_DDRCLK_100		0x1
24 #define QIXIS_DDRCLK_125		0x2
25 #define QIXIS_DDRCLK_133		0x3
26 
27 /* BRDCFG2 - SD clock*/
28 #define QIXIS_SDCLK1_100		0x0
29 #define QIXIS_SDCLK1_125		0x1
30 #define QIXIS_SDCLK1_165		0x2
31 #define QIXIS_SDCLK1_100_SP		0x3
32 
33 #define BRDCFG4_EMISEL_MASK		0xE0
34 #define BRDCFG4_EMISEL_SHIFT		5
35 #define BRDCFG9_SFPTX_MASK		0x10
36 #define BRDCFG9_SFPTX_SHIFT		4
37 
38 /* Definitions of QIXIS Registers for LS1088ARDB */
39 
40 /* BRDCFG5 */
41 #define BRDCFG5_SPISDHC_MASK		0x0C
42 #define BRDCFG5_FORCE_SD		0x08
43 
44 #endif
45