1 /* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1088AQDS_QIXIS_H__ 8 #define __LS1088AQDS_QIXIS_H__ 9 10 /* Definitions of QIXIS Registers for LS1088AQDS */ 11 12 /* SYSCLK */ 13 #define QIXIS_SYSCLK_66 0x0 14 #define QIXIS_SYSCLK_83 0x1 15 #define QIXIS_SYSCLK_100 0x2 16 #define QIXIS_SYSCLK_125 0x3 17 #define QIXIS_SYSCLK_133 0x4 18 #define QIXIS_SYSCLK_150 0x5 19 #define QIXIS_SYSCLK_160 0x6 20 #define QIXIS_SYSCLK_166 0x7 21 22 /* DDRCLK */ 23 #define QIXIS_DDRCLK_66 0x0 24 #define QIXIS_DDRCLK_100 0x1 25 #define QIXIS_DDRCLK_125 0x2 26 #define QIXIS_DDRCLK_133 0x3 27 28 /* BRDCFG2 - SD clock*/ 29 #define QIXIS_SDCLK1_100 0x0 30 #define QIXIS_SDCLK1_125 0x1 31 #define QIXIS_SDCLK1_165 0x2 32 #define QIXIS_SDCLK1_100_SP 0x3 33 34 #define BRDCFG4_EMISEL_MASK 0xE0 35 #define BRDCFG4_EMISEL_SHIFT 5 36 #define BRDCFG9_SFPTX_MASK 0x10 37 #define BRDCFG9_SFPTX_SHIFT 4 38 39 #endif 40