1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2017 NXP
4  */
5 #include <common.h>
6 #include <i2c.h>
7 #include <malloc.h>
8 #include <errno.h>
9 #include <netdev.h>
10 #include <fsl_ifc.h>
11 #include <fsl_ddr.h>
12 #include <fsl_sec.h>
13 #include <asm/io.h>
14 #include <fdt_support.h>
15 #include <linux/libfdt.h>
16 #include <fsl-mc/fsl_mc.h>
17 #include <environment.h>
18 #include <asm/arch-fsl-layerscape/soc.h>
19 #include <asm/arch/ppa.h>
20 #include <hwconfig.h>
21 #include <asm/arch/fsl_serdes.h>
22 #include <asm/arch/soc.h>
23 
24 #include "../common/qixis.h"
25 #include "ls1088a_qixis.h"
26 #include "../common/vid.h"
27 #include <fsl_immap.h>
28 
29 DECLARE_GLOBAL_DATA_PTR;
30 
31 int board_early_init_f(void)
32 {
33 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
34 	i2c_early_init_f();
35 #endif
36 	fsl_lsch3_early_init_f();
37 	return 0;
38 }
39 
40 #ifdef CONFIG_FSL_QIXIS
41 unsigned long long get_qixis_addr(void)
42 {
43 	unsigned long long addr;
44 
45 	if (gd->flags & GD_FLG_RELOC)
46 		addr = QIXIS_BASE_PHYS;
47 	else
48 		addr = QIXIS_BASE_PHYS_EARLY;
49 
50 	/*
51 	 * IFC address under 256MB is mapped to 0x30000000, any address above
52 	 * is mapped to 0x5_10000000 up to 4GB.
53 	 */
54 	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
55 
56 	return addr;
57 }
58 #endif
59 
60 #if defined(CONFIG_VID)
61 int init_func_vid(void)
62 {
63 	if (adjust_vdd(0) < 0)
64 		printf("core voltage not adjusted\n");
65 
66 	return 0;
67 }
68 #endif
69 
70 #if !defined(CONFIG_SPL_BUILD)
71 int checkboard(void)
72 {
73 	char buf[64];
74 	u8 sw;
75 	static const char *const freq[] = {"100", "125", "156.25",
76 					    "100 separate SSCG"};
77 	int clock;
78 
79 #ifdef CONFIG_TARGET_LS1088AQDS
80 	printf("Board: LS1088A-QDS, ");
81 #else
82 	printf("Board: LS1088A-RDB, ");
83 #endif
84 
85 	sw = QIXIS_READ(arch);
86 	printf("Board Arch: V%d, ", sw >> 4);
87 
88 #ifdef CONFIG_TARGET_LS1088AQDS
89 	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
90 #else
91 	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
92 #endif
93 
94 	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
95 
96 	sw = QIXIS_READ(brdcfg[0]);
97 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
98 
99 #ifdef CONFIG_SD_BOOT
100 	puts("SD card\n");
101 #endif
102 	switch (sw) {
103 #ifdef CONFIG_TARGET_LS1088AQDS
104 	case 0:
105 	case 1:
106 	case 2:
107 	case 3:
108 	case 4:
109 	case 5:
110 	case 6:
111 	case 7:
112 		printf("vBank: %d\n", sw);
113 		break;
114 	case 8:
115 		puts("PromJet\n");
116 		break;
117 	case 15:
118 		puts("IFCCard\n");
119 		break;
120 	case 14:
121 #else
122 	case 0:
123 #endif
124 		puts("QSPI:");
125 		sw = QIXIS_READ(brdcfg[0]);
126 		sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
127 		if (sw == 0 || sw == 4)
128 			puts("0\n");
129 		else if (sw == 1)
130 			puts("1\n");
131 		else
132 			puts("EMU\n");
133 		break;
134 
135 	default:
136 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
137 		break;
138 	}
139 
140 #ifdef CONFIG_TARGET_LS1088AQDS
141 	printf("FPGA: v%d (%s), build %d",
142 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
143 	       (int)qixis_read_minor());
144 	/* the timestamp string contains "\n" at the end */
145 	printf(" on %s", qixis_read_time(buf));
146 #else
147 	printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
148 #endif
149 
150 	/*
151 	 * Display the actual SERDES reference clocks as configured by the
152 	 * dip switches on the board.  Note that the SWx registers could
153 	 * technically be set to force the reference clocks to match the
154 	 * values that the SERDES expects (or vice versa).  For now, however,
155 	 * we just display both values and hope the user notices when they
156 	 * don't match.
157 	 */
158 	puts("SERDES1 Reference : ");
159 	sw = QIXIS_READ(brdcfg[2]);
160 	clock = (sw >> 6) & 3;
161 	printf("Clock1 = %sMHz ", freq[clock]);
162 	clock = (sw >> 4) & 3;
163 	printf("Clock2 = %sMHz", freq[clock]);
164 
165 	puts("\nSERDES2 Reference : ");
166 	clock = (sw >> 2) & 3;
167 	printf("Clock1 = %sMHz ", freq[clock]);
168 	clock = (sw >> 0) & 3;
169 	printf("Clock2 = %sMHz\n", freq[clock]);
170 
171 	return 0;
172 }
173 #endif
174 
175 bool if_board_diff_clk(void)
176 {
177 #ifdef CONFIG_TARGET_LS1088AQDS
178 	u8 diff_conf = QIXIS_READ(brdcfg[11]);
179 	return diff_conf & 0x40;
180 #else
181 	u8 diff_conf = QIXIS_READ(dutcfg[11]);
182 	return diff_conf & 0x80;
183 #endif
184 }
185 
186 unsigned long get_board_sys_clk(void)
187 {
188 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
189 
190 	switch (sysclk_conf & 0x0f) {
191 	case QIXIS_SYSCLK_83:
192 		return 83333333;
193 	case QIXIS_SYSCLK_100:
194 		return 100000000;
195 	case QIXIS_SYSCLK_125:
196 		return 125000000;
197 	case QIXIS_SYSCLK_133:
198 		return 133333333;
199 	case QIXIS_SYSCLK_150:
200 		return 150000000;
201 	case QIXIS_SYSCLK_160:
202 		return 160000000;
203 	case QIXIS_SYSCLK_166:
204 		return 166666666;
205 	}
206 
207 	return 66666666;
208 }
209 
210 unsigned long get_board_ddr_clk(void)
211 {
212 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
213 
214 	if (if_board_diff_clk())
215 		return get_board_sys_clk();
216 	switch ((ddrclk_conf & 0x30) >> 4) {
217 	case QIXIS_DDRCLK_100:
218 		return 100000000;
219 	case QIXIS_DDRCLK_125:
220 		return 125000000;
221 	case QIXIS_DDRCLK_133:
222 		return 133333333;
223 	}
224 
225 	return 66666666;
226 }
227 
228 int select_i2c_ch_pca9547(u8 ch)
229 {
230 	int ret;
231 
232 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
233 	if (ret) {
234 		puts("PCA: failed to select proper channel\n");
235 		return ret;
236 	}
237 
238 	return 0;
239 }
240 
241 #if !defined(CONFIG_SPL_BUILD)
242 void board_retimer_init(void)
243 {
244 	u8 reg;
245 
246 	/* Retimer is connected to I2C1_CH5 */
247 	select_i2c_ch_pca9547(I2C_MUX_CH5);
248 
249 	/* Access to Control/Shared register */
250 	reg = 0x0;
251 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
252 
253 	/* Read device revision and ID */
254 	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
255 	debug("Retimer version id = 0x%x\n", reg);
256 
257 	/* Enable Broadcast. All writes target all channel register sets */
258 	reg = 0x0c;
259 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
260 
261 	/* Reset Channel Registers */
262 	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
263 	reg |= 0x4;
264 	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
265 
266 	/* Set data rate as 10.3125 Gbps */
267 	reg = 0x90;
268 	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
269 	reg = 0xb3;
270 	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
271 	reg = 0x90;
272 	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
273 	reg = 0xb3;
274 	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
275 	reg = 0xcd;
276 	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
277 
278 	/* Select VCO Divider to full rate (000) */
279 	i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
280 	reg &= 0x0f;
281 	reg |= 0x70;
282 	i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
283 
284 #ifdef	CONFIG_TARGET_LS1088AQDS
285 	/* Retimer is connected to I2C1_CH5 */
286 	select_i2c_ch_pca9547(I2C_MUX_CH5);
287 
288 	/* Access to Control/Shared register */
289 	reg = 0x0;
290 	i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
291 
292 	/* Read device revision and ID */
293 	i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
294 	debug("Retimer version id = 0x%x\n", reg);
295 
296 	/* Enable Broadcast. All writes target all channel register sets */
297 	reg = 0x0c;
298 	i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
299 
300 	/* Reset Channel Registers */
301 	i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
302 	reg |= 0x4;
303 	i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
304 
305 	/* Set data rate as 10.3125 Gbps */
306 	reg = 0x90;
307 	i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
308 	reg = 0xb3;
309 	i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
310 	reg = 0x90;
311 	i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
312 	reg = 0xb3;
313 	i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
314 	reg = 0xcd;
315 	i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
316 
317 	/* Select VCO Divider to full rate (000) */
318 	i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
319 	reg &= 0x0f;
320 	reg |= 0x70;
321 	i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
322 #endif
323 	/*return the default channel*/
324 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
325 }
326 
327 #ifdef CONFIG_MISC_INIT_R
328 int misc_init_r(void)
329 {
330 #ifdef CONFIG_TARGET_LS1088ARDB
331 	u8 brdcfg5;
332 
333 	if (hwconfig("esdhc-force-sd")) {
334 		brdcfg5 = QIXIS_READ(brdcfg[5]);
335 		brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
336 		brdcfg5 |= BRDCFG5_FORCE_SD;
337 		QIXIS_WRITE(brdcfg[5], brdcfg5);
338 	}
339 #endif
340 	return 0;
341 }
342 #endif
343 #endif
344 
345 int i2c_multiplexer_select_vid_channel(u8 channel)
346 {
347 	return select_i2c_ch_pca9547(channel);
348 }
349 
350 #ifdef CONFIG_TARGET_LS1088AQDS
351 /* read the current value(SVDD) of the LTM Regulator Voltage */
352 int get_serdes_volt(void)
353 {
354 	int  ret, vcode = 0;
355 	u8 chan = PWM_CHANNEL0;
356 
357 	/* Select the PAGE 0 using PMBus commands PAGE for VDD */
358 	ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
359 			PMBUS_CMD_PAGE, 1, &chan, 1);
360 	if (ret) {
361 		printf("VID: failed to select VDD Page 0\n");
362 		return ret;
363 	}
364 
365 	/* Read the output voltage using PMBus command READ_VOUT */
366 	ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
367 		       PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
368 	if (ret) {
369 		printf("VID: failed to read the volatge\n");
370 		return ret;
371 	}
372 
373 	return vcode;
374 }
375 
376 int set_serdes_volt(int svdd)
377 {
378 	int ret, vdd_last;
379 	u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
380 			svdd & 0xFF, (svdd & 0xFF00) >> 8};
381 
382 	/* Write the desired voltage code to the SVDD regulator */
383 	ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
384 			PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
385 	if (ret) {
386 		printf("VID: I2C failed to write to the volatge regulator\n");
387 		return -1;
388 	}
389 
390 	/* Wait for the volatge to get to the desired value */
391 	do {
392 		vdd_last = get_serdes_volt();
393 		if (vdd_last < 0) {
394 			printf("VID: Couldn't read sensor abort VID adjust\n");
395 			return -1;
396 		}
397 	} while (vdd_last != svdd);
398 
399 	return 1;
400 }
401 #else
402 int get_serdes_volt(void)
403 {
404 	return 0;
405 }
406 
407 int set_serdes_volt(int svdd)
408 {
409 	int ret;
410 	u8 brdcfg4;
411 
412 	printf("SVDD changing of RDB\n");
413 
414 	/* Read the BRDCFG54 via CLPD */
415 	ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
416 		       QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
417 	if (ret) {
418 		printf("VID: I2C failed to read the CPLD BRDCFG4\n");
419 		return -1;
420 	}
421 
422 	brdcfg4 = brdcfg4 | 0x08;
423 
424 	/* Write to the BRDCFG4 */
425 	ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
426 			QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
427 	if (ret) {
428 		debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
429 		return -1;
430 	}
431 
432 	/* Wait for the volatge to get to the desired value */
433 	udelay(10000);
434 
435 	return 1;
436 }
437 #endif
438 
439 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
440 int board_adjust_vdd(int vdd)
441 {
442 	int ret = 0;
443 
444 	debug("%s: vdd = %d\n", __func__, vdd);
445 
446 	/* Special settings to be performed when voltage is 900mV */
447 	if (vdd == 900) {
448 		ret = setup_serdes_volt(vdd);
449 		if (ret < 0) {
450 			ret = -1;
451 			goto exit;
452 		}
453 	}
454 exit:
455 	return ret;
456 }
457 
458 #if !defined(CONFIG_SPL_BUILD)
459 int board_init(void)
460 {
461 	init_final_memctl_regs();
462 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
463 	u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
464 #endif
465 
466 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
467 	board_retimer_init();
468 
469 #ifdef CONFIG_ENV_IS_NOWHERE
470 	gd->env_addr = (ulong)&default_environment[0];
471 #endif
472 
473 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
474 	/* invert AQR105 IRQ pins polarity */
475 	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
476 #endif
477 
478 #ifdef CONFIG_FSL_CAAM
479 	sec_init();
480 #endif
481 #ifdef CONFIG_FSL_LS_PPA
482 	ppa_init();
483 #endif
484 	return 0;
485 }
486 
487 void detail_board_ddr_info(void)
488 {
489 	puts("\nDDR    ");
490 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
491 	print_ddr_info(0);
492 }
493 
494 #if defined(CONFIG_ARCH_MISC_INIT)
495 int arch_misc_init(void)
496 {
497 	return 0;
498 }
499 #endif
500 
501 #ifdef CONFIG_FSL_MC_ENET
502 void fdt_fixup_board_enet(void *fdt)
503 {
504 	int offset;
505 
506 	offset = fdt_path_offset(fdt, "/fsl-mc");
507 
508 	if (offset < 0)
509 		offset = fdt_path_offset(fdt, "/fsl,dprc@0");
510 
511 	if (offset < 0) {
512 		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
513 		       __func__, offset);
514 		return;
515 	}
516 
517 	if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
518 		fdt_status_okay(fdt, offset);
519 	else
520 		fdt_status_fail(fdt, offset);
521 }
522 #endif
523 
524 #ifdef CONFIG_OF_BOARD_SETUP
525 void fsl_fdt_fixup_flash(void *fdt)
526 {
527 	int offset;
528 
529 /*
530  * IFC-NOR and QSPI are muxed on SoC.
531  * So disable IFC node in dts if QSPI is enabled or
532  * disable QSPI node in dts in case QSPI is not enabled.
533  */
534 
535 #ifdef CONFIG_FSL_QSPI
536 	offset = fdt_path_offset(fdt, "/soc/ifc/nor");
537 
538 	if (offset < 0)
539 		offset = fdt_path_offset(fdt, "/ifc/nor");
540 #else
541 	offset = fdt_path_offset(fdt, "/soc/quadspi");
542 
543 	if (offset < 0)
544 		offset = fdt_path_offset(fdt, "/quadspi");
545 #endif
546 	if (offset < 0)
547 		return;
548 
549 	fdt_status_disabled(fdt, offset);
550 }
551 
552 int ft_board_setup(void *blob, bd_t *bd)
553 {
554 	int err, i;
555 	u64 base[CONFIG_NR_DRAM_BANKS];
556 	u64 size[CONFIG_NR_DRAM_BANKS];
557 
558 	ft_cpu_setup(blob, bd);
559 
560 	/* fixup DT for the two GPP DDR banks */
561 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
562 		base[i] = gd->bd->bi_dram[i].start;
563 		size[i] = gd->bd->bi_dram[i].size;
564 	}
565 
566 #ifdef CONFIG_RESV_RAM
567 	/* reduce size if reserved memory is within this bank */
568 	if (gd->arch.resv_ram >= base[0] &&
569 	    gd->arch.resv_ram < base[0] + size[0])
570 		size[0] = gd->arch.resv_ram - base[0];
571 	else if (gd->arch.resv_ram >= base[1] &&
572 		 gd->arch.resv_ram < base[1] + size[1])
573 		size[1] = gd->arch.resv_ram - base[1];
574 #endif
575 
576 	fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
577 
578 	fsl_fdt_fixup_flash(blob);
579 
580 #ifdef CONFIG_FSL_MC_ENET
581 	fdt_fixup_board_enet(blob);
582 	err = fsl_mc_ldpaa_exit(bd);
583 	if (err)
584 		return err;
585 #endif
586 
587 	return 0;
588 }
589 #endif
590 #endif /* defined(CONFIG_SPL_BUILD) */
591