1 /* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <i2c.h> 8 #include <malloc.h> 9 #include <errno.h> 10 #include <netdev.h> 11 #include <fsl_ifc.h> 12 #include <fsl_ddr.h> 13 #include <fsl_sec.h> 14 #include <asm/io.h> 15 #include <fdt_support.h> 16 #include <libfdt.h> 17 #include <fsl-mc/fsl_mc.h> 18 #include <environment.h> 19 #include <asm/arch-fsl-layerscape/soc.h> 20 #include <asm/arch/ppa.h> 21 #include <hwconfig.h> 22 23 #include "../common/qixis.h" 24 #include "ls1088a_qixis.h" 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 int board_early_init_f(void) 29 { 30 fsl_lsch3_early_init_f(); 31 return 0; 32 } 33 34 #ifdef CONFIG_FSL_QIXIS 35 unsigned long long get_qixis_addr(void) 36 { 37 unsigned long long addr; 38 39 if (gd->flags & GD_FLG_RELOC) 40 addr = QIXIS_BASE_PHYS; 41 else 42 addr = QIXIS_BASE_PHYS_EARLY; 43 44 /* 45 * IFC address under 256MB is mapped to 0x30000000, any address above 46 * is mapped to 0x5_10000000 up to 4GB. 47 */ 48 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; 49 50 return addr; 51 } 52 #endif 53 54 #if !defined(CONFIG_SPL_BUILD) 55 int checkboard(void) 56 { 57 char buf[64]; 58 u8 sw; 59 static const char *const freq[] = {"100", "125", "156.25", 60 "100 separate SSCG"}; 61 int clock; 62 63 #ifdef CONFIG_TARGET_LS1088AQDS 64 printf("Board: LS1088A-QDS, "); 65 #else 66 printf("Board: LS1088A-RDB, "); 67 #endif 68 69 sw = QIXIS_READ(arch); 70 printf("Board Arch: V%d, ", sw >> 4); 71 72 #ifdef CONFIG_TARGET_LS1088AQDS 73 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); 74 #else 75 printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); 76 #endif 77 78 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); 79 80 sw = QIXIS_READ(brdcfg[0]); 81 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 82 83 #ifdef CONFIG_SD_BOOT 84 puts("SD card\n"); 85 #endif 86 switch (sw) { 87 #ifdef CONFIG_TARGET_LS1088AQDS 88 case 0: 89 case 1: 90 case 2: 91 case 3: 92 case 4: 93 case 5: 94 case 6: 95 case 7: 96 printf("vBank: %d\n", sw); 97 break; 98 case 8: 99 puts("PromJet\n"); 100 break; 101 case 15: 102 puts("IFCCard\n"); 103 break; 104 case 14: 105 #else 106 case 0: 107 #endif 108 puts("QSPI:"); 109 sw = QIXIS_READ(brdcfg[0]); 110 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT; 111 if (sw == 0 || sw == 4) 112 puts("0\n"); 113 else if (sw == 1) 114 puts("1\n"); 115 else 116 puts("EMU\n"); 117 break; 118 119 default: 120 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 121 break; 122 } 123 124 #ifdef CONFIG_TARGET_LS1088AQDS 125 printf("FPGA: v%d (%s), build %d", 126 (int)QIXIS_READ(scver), qixis_read_tag(buf), 127 (int)qixis_read_minor()); 128 /* the timestamp string contains "\n" at the end */ 129 printf(" on %s", qixis_read_time(buf)); 130 #else 131 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); 132 #endif 133 134 /* 135 * Display the actual SERDES reference clocks as configured by the 136 * dip switches on the board. Note that the SWx registers could 137 * technically be set to force the reference clocks to match the 138 * values that the SERDES expects (or vice versa). For now, however, 139 * we just display both values and hope the user notices when they 140 * don't match. 141 */ 142 puts("SERDES1 Reference : "); 143 sw = QIXIS_READ(brdcfg[2]); 144 clock = (sw >> 6) & 3; 145 printf("Clock1 = %sMHz ", freq[clock]); 146 clock = (sw >> 4) & 3; 147 printf("Clock2 = %sMHz", freq[clock]); 148 149 puts("\nSERDES2 Reference : "); 150 clock = (sw >> 2) & 3; 151 printf("Clock1 = %sMHz ", freq[clock]); 152 clock = (sw >> 0) & 3; 153 printf("Clock2 = %sMHz\n", freq[clock]); 154 155 return 0; 156 } 157 158 bool if_board_diff_clk(void) 159 { 160 #ifdef CONFIG_TARGET_LS1088AQDS 161 u8 diff_conf = QIXIS_READ(brdcfg[11]); 162 return diff_conf & 0x40; 163 #else 164 u8 diff_conf = QIXIS_READ(dutcfg[11]); 165 return diff_conf & 0x80; 166 #endif 167 } 168 169 unsigned long get_board_sys_clk(void) 170 { 171 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 172 173 switch (sysclk_conf & 0x0f) { 174 case QIXIS_SYSCLK_83: 175 return 83333333; 176 case QIXIS_SYSCLK_100: 177 return 100000000; 178 case QIXIS_SYSCLK_125: 179 return 125000000; 180 case QIXIS_SYSCLK_133: 181 return 133333333; 182 case QIXIS_SYSCLK_150: 183 return 150000000; 184 case QIXIS_SYSCLK_160: 185 return 160000000; 186 case QIXIS_SYSCLK_166: 187 return 166666666; 188 } 189 190 return 66666666; 191 } 192 193 unsigned long get_board_ddr_clk(void) 194 { 195 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 196 197 if (if_board_diff_clk()) 198 return get_board_sys_clk(); 199 switch ((ddrclk_conf & 0x30) >> 4) { 200 case QIXIS_DDRCLK_100: 201 return 100000000; 202 case QIXIS_DDRCLK_125: 203 return 125000000; 204 case QIXIS_DDRCLK_133: 205 return 133333333; 206 } 207 208 return 66666666; 209 } 210 211 int select_i2c_ch_pca9547(u8 ch) 212 { 213 int ret; 214 215 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 216 if (ret) { 217 puts("PCA: failed to select proper channel\n"); 218 return ret; 219 } 220 221 return 0; 222 } 223 224 void board_retimer_init(void) 225 { 226 u8 reg; 227 228 /* Retimer is connected to I2C1_CH5 */ 229 select_i2c_ch_pca9547(I2C_MUX_CH5); 230 231 /* Access to Control/Shared register */ 232 reg = 0x0; 233 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 234 235 /* Read device revision and ID */ 236 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); 237 debug("Retimer version id = 0x%x\n", reg); 238 239 /* Enable Broadcast. All writes target all channel register sets */ 240 reg = 0x0c; 241 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 242 243 /* Reset Channel Registers */ 244 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); 245 reg |= 0x4; 246 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); 247 248 /* Set data rate as 10.3125 Gbps */ 249 reg = 0x90; 250 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); 251 reg = 0xb3; 252 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); 253 reg = 0x90; 254 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); 255 reg = 0xb3; 256 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); 257 reg = 0xcd; 258 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); 259 260 /* Select VCO Divider to full rate (000) */ 261 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); 262 reg &= 0x0f; 263 reg |= 0x70; 264 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); 265 266 #ifdef CONFIG_TARGET_LS1088AQDS 267 /* Retimer is connected to I2C1_CH5 */ 268 select_i2c_ch_pca9547(I2C_MUX_CH5); 269 270 /* Access to Control/Shared register */ 271 reg = 0x0; 272 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); 273 274 /* Read device revision and ID */ 275 i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1); 276 debug("Retimer version id = 0x%x\n", reg); 277 278 /* Enable Broadcast. All writes target all channel register sets */ 279 reg = 0x0c; 280 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); 281 282 /* Reset Channel Registers */ 283 i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1); 284 reg |= 0x4; 285 i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1); 286 287 /* Set data rate as 10.3125 Gbps */ 288 reg = 0x90; 289 i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1); 290 reg = 0xb3; 291 i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1); 292 reg = 0x90; 293 i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1); 294 reg = 0xb3; 295 i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1); 296 reg = 0xcd; 297 i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1); 298 299 /* Select VCO Divider to full rate (000) */ 300 i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); 301 reg &= 0x0f; 302 reg |= 0x70; 303 i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); 304 #endif 305 /*return the default channel*/ 306 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 307 } 308 309 #ifdef CONFIG_MISC_INIT_R 310 int misc_init_r(void) 311 { 312 #ifdef CONFIG_TARGET_LS1088ARDB 313 u8 brdcfg5; 314 315 if (hwconfig("esdhc-force-sd")) { 316 brdcfg5 = QIXIS_READ(brdcfg[5]); 317 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK; 318 brdcfg5 |= BRDCFG5_FORCE_SD; 319 QIXIS_WRITE(brdcfg[5], brdcfg5); 320 } 321 #endif 322 return 0; 323 } 324 #endif 325 326 int board_init(void) 327 { 328 init_final_memctl_regs(); 329 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) 330 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; 331 #endif 332 333 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 334 board_retimer_init(); 335 336 #ifdef CONFIG_ENV_IS_NOWHERE 337 gd->env_addr = (ulong)&default_environment[0]; 338 #endif 339 340 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) 341 /* invert AQR105 IRQ pins polarity */ 342 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK); 343 #endif 344 345 #ifdef CONFIG_FSL_CAAM 346 sec_init(); 347 #endif 348 #ifdef CONFIG_FSL_LS_PPA 349 ppa_init(); 350 #endif 351 return 0; 352 } 353 354 void detail_board_ddr_info(void) 355 { 356 puts("\nDDR "); 357 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); 358 print_ddr_info(0); 359 } 360 361 #if defined(CONFIG_ARCH_MISC_INIT) 362 int arch_misc_init(void) 363 { 364 return 0; 365 } 366 #endif 367 368 #ifdef CONFIG_FSL_MC_ENET 369 void fdt_fixup_board_enet(void *fdt) 370 { 371 int offset; 372 373 offset = fdt_path_offset(fdt, "/fsl-mc"); 374 375 if (offset < 0) 376 offset = fdt_path_offset(fdt, "/fsl,dprc@0"); 377 378 if (offset < 0) { 379 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", 380 __func__, offset); 381 return; 382 } 383 384 if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) 385 fdt_status_okay(fdt, offset); 386 else 387 fdt_status_fail(fdt, offset); 388 } 389 #endif 390 391 #ifdef CONFIG_OF_BOARD_SETUP 392 void fsl_fdt_fixup_flash(void *fdt) 393 { 394 int offset; 395 396 /* 397 * IFC-NOR and QSPI are muxed on SoC. 398 * So disable IFC node in dts if QSPI is enabled or 399 * disable QSPI node in dts in case QSPI is not enabled. 400 */ 401 402 #ifdef CONFIG_FSL_QSPI 403 offset = fdt_path_offset(fdt, "/soc/ifc/nor"); 404 405 if (offset < 0) 406 offset = fdt_path_offset(fdt, "/ifc/nor"); 407 #else 408 offset = fdt_path_offset(fdt, "/soc/quadspi"); 409 410 if (offset < 0) 411 offset = fdt_path_offset(fdt, "/quadspi"); 412 #endif 413 if (offset < 0) 414 return; 415 416 fdt_status_disabled(fdt, offset); 417 } 418 419 int ft_board_setup(void *blob, bd_t *bd) 420 { 421 int err, i; 422 u64 base[CONFIG_NR_DRAM_BANKS]; 423 u64 size[CONFIG_NR_DRAM_BANKS]; 424 425 ft_cpu_setup(blob, bd); 426 427 /* fixup DT for the two GPP DDR banks */ 428 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 429 base[i] = gd->bd->bi_dram[i].start; 430 size[i] = gd->bd->bi_dram[i].size; 431 } 432 433 #ifdef CONFIG_RESV_RAM 434 /* reduce size if reserved memory is within this bank */ 435 if (gd->arch.resv_ram >= base[0] && 436 gd->arch.resv_ram < base[0] + size[0]) 437 size[0] = gd->arch.resv_ram - base[0]; 438 else if (gd->arch.resv_ram >= base[1] && 439 gd->arch.resv_ram < base[1] + size[1]) 440 size[1] = gd->arch.resv_ram - base[1]; 441 #endif 442 443 fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); 444 445 fsl_fdt_fixup_flash(blob); 446 447 #ifdef CONFIG_FSL_MC_ENET 448 fdt_fixup_board_enet(blob); 449 err = fsl_mc_ldpaa_exit(bd); 450 if (err) 451 return err; 452 #endif 453 454 return 0; 455 } 456 #endif 457 #endif /* defined(CONFIG_SPL_BUILD) */ 458