1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2017-2018 NXP 4 */ 5 #include <common.h> 6 #include <i2c.h> 7 #include <malloc.h> 8 #include <errno.h> 9 #include <netdev.h> 10 #include <fsl_ifc.h> 11 #include <fsl_ddr.h> 12 #include <fsl_sec.h> 13 #include <asm/io.h> 14 #include <fdt_support.h> 15 #include <linux/libfdt.h> 16 #include <fsl-mc/fsl_mc.h> 17 #include <environment.h> 18 #include <asm/arch-fsl-layerscape/soc.h> 19 #include <asm/arch/ppa.h> 20 #include <hwconfig.h> 21 #include <asm/arch/fsl_serdes.h> 22 #include <asm/arch/soc.h> 23 24 #include "../common/qixis.h" 25 #include "ls1088a_qixis.h" 26 #include "../common/vid.h" 27 #include <fsl_immap.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #ifdef CONFIG_TARGET_LS1088AQDS 32 #ifdef CONFIG_TFABOOT 33 struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { 34 { 35 "nor0", 36 CONFIG_SYS_NOR0_CSPR_EARLY, 37 CONFIG_SYS_NOR0_CSPR_EXT, 38 CONFIG_SYS_NOR_AMASK, 39 CONFIG_SYS_NOR_CSOR, 40 { 41 CONFIG_SYS_NOR_FTIM0, 42 CONFIG_SYS_NOR_FTIM1, 43 CONFIG_SYS_NOR_FTIM2, 44 CONFIG_SYS_NOR_FTIM3 45 }, 46 0, 47 CONFIG_SYS_NOR0_CSPR, 48 0, 49 }, 50 { 51 "nor1", 52 CONFIG_SYS_NOR1_CSPR_EARLY, 53 CONFIG_SYS_NOR0_CSPR_EXT, 54 CONFIG_SYS_NOR_AMASK_EARLY, 55 CONFIG_SYS_NOR_CSOR, 56 { 57 CONFIG_SYS_NOR_FTIM0, 58 CONFIG_SYS_NOR_FTIM1, 59 CONFIG_SYS_NOR_FTIM2, 60 CONFIG_SYS_NOR_FTIM3 61 }, 62 0, 63 CONFIG_SYS_NOR1_CSPR, 64 CONFIG_SYS_NOR_AMASK, 65 }, 66 { 67 "nand", 68 CONFIG_SYS_NAND_CSPR, 69 CONFIG_SYS_NAND_CSPR_EXT, 70 CONFIG_SYS_NAND_AMASK, 71 CONFIG_SYS_NAND_CSOR, 72 { 73 CONFIG_SYS_NAND_FTIM0, 74 CONFIG_SYS_NAND_FTIM1, 75 CONFIG_SYS_NAND_FTIM2, 76 CONFIG_SYS_NAND_FTIM3 77 }, 78 }, 79 { 80 "fpga", 81 CONFIG_SYS_FPGA_CSPR, 82 CONFIG_SYS_FPGA_CSPR_EXT, 83 SYS_FPGA_AMASK, 84 CONFIG_SYS_FPGA_CSOR, 85 { 86 SYS_FPGA_CS_FTIM0, 87 SYS_FPGA_CS_FTIM1, 88 SYS_FPGA_CS_FTIM2, 89 SYS_FPGA_CS_FTIM3 90 }, 91 0, 92 SYS_FPGA_CSPR_FINAL, 93 0, 94 } 95 }; 96 97 struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { 98 { 99 "nand", 100 CONFIG_SYS_NAND_CSPR, 101 CONFIG_SYS_NAND_CSPR_EXT, 102 CONFIG_SYS_NAND_AMASK, 103 CONFIG_SYS_NAND_CSOR, 104 { 105 CONFIG_SYS_NAND_FTIM0, 106 CONFIG_SYS_NAND_FTIM1, 107 CONFIG_SYS_NAND_FTIM2, 108 CONFIG_SYS_NAND_FTIM3 109 }, 110 }, 111 { 112 "reserved", 113 }, 114 { 115 "fpga", 116 CONFIG_SYS_FPGA_CSPR, 117 CONFIG_SYS_FPGA_CSPR_EXT, 118 SYS_FPGA_AMASK, 119 CONFIG_SYS_FPGA_CSOR, 120 { 121 SYS_FPGA_CS_FTIM0, 122 SYS_FPGA_CS_FTIM1, 123 SYS_FPGA_CS_FTIM2, 124 SYS_FPGA_CS_FTIM3 125 }, 126 0, 127 SYS_FPGA_CSPR_FINAL, 128 0, 129 } 130 }; 131 132 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) 133 { 134 enum boot_src src = get_boot_src(); 135 136 if (src == BOOT_SOURCE_QSPI_NOR) 137 regs_info->regs = ifc_cfg_qspi_nor_boot; 138 else 139 regs_info->regs = ifc_cfg_ifc_nor_boot; 140 141 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; 142 } 143 #endif /* CONFIG_TFABOOT */ 144 #endif /* CONFIG_TARGET_LS1088AQDS */ 145 146 int board_early_init_f(void) 147 { 148 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS) 149 i2c_early_init_f(); 150 #endif 151 fsl_lsch3_early_init_f(); 152 return 0; 153 } 154 155 #ifdef CONFIG_FSL_QIXIS 156 unsigned long long get_qixis_addr(void) 157 { 158 unsigned long long addr; 159 160 if (gd->flags & GD_FLG_RELOC) 161 addr = QIXIS_BASE_PHYS; 162 else 163 addr = QIXIS_BASE_PHYS_EARLY; 164 165 /* 166 * IFC address under 256MB is mapped to 0x30000000, any address above 167 * is mapped to 0x5_10000000 up to 4GB. 168 */ 169 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; 170 171 return addr; 172 } 173 #endif 174 175 #if defined(CONFIG_VID) 176 int init_func_vid(void) 177 { 178 if (adjust_vdd(0) < 0) 179 printf("core voltage not adjusted\n"); 180 181 return 0; 182 } 183 #endif 184 185 int is_pb_board(void) 186 { 187 u8 board_id; 188 189 board_id = QIXIS_READ(id); 190 if (board_id == LS1088ARDB_PB_BOARD) 191 return 1; 192 else 193 return 0; 194 } 195 196 int fixup_ls1088ardb_pb_banner(void *fdt) 197 { 198 fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board"); 199 200 return 0; 201 } 202 203 #if !defined(CONFIG_SPL_BUILD) 204 int checkboard(void) 205 { 206 #ifdef CONFIG_TFABOOT 207 enum boot_src src = get_boot_src(); 208 #endif 209 char buf[64]; 210 u8 sw; 211 static const char *const freq[] = {"100", "125", "156.25", 212 "100 separate SSCG"}; 213 int clock; 214 215 #ifdef CONFIG_TARGET_LS1088AQDS 216 printf("Board: LS1088A-QDS, "); 217 #else 218 if (is_pb_board()) 219 printf("Board: LS1088ARDB-PB, "); 220 else 221 printf("Board: LS1088A-RDB, "); 222 #endif 223 224 sw = QIXIS_READ(arch); 225 printf("Board Arch: V%d, ", sw >> 4); 226 227 #ifdef CONFIG_TARGET_LS1088AQDS 228 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); 229 #else 230 printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); 231 #endif 232 233 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); 234 235 sw = QIXIS_READ(brdcfg[0]); 236 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 237 238 #ifdef CONFIG_TFABOOT 239 if (src == BOOT_SOURCE_SD_MMC) 240 puts("SD card\n"); 241 #else 242 #ifdef CONFIG_SD_BOOT 243 puts("SD card\n"); 244 #endif 245 #endif /* CONFIG_TFABOOT */ 246 switch (sw) { 247 #ifdef CONFIG_TARGET_LS1088AQDS 248 case 0: 249 case 1: 250 case 2: 251 case 3: 252 case 4: 253 case 5: 254 case 6: 255 case 7: 256 printf("vBank: %d\n", sw); 257 break; 258 case 8: 259 puts("PromJet\n"); 260 break; 261 case 15: 262 puts("IFCCard\n"); 263 break; 264 case 14: 265 #else 266 case 0: 267 #endif 268 puts("QSPI:"); 269 sw = QIXIS_READ(brdcfg[0]); 270 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT; 271 if (sw == 0 || sw == 4) 272 puts("0\n"); 273 else if (sw == 1) 274 puts("1\n"); 275 else 276 puts("EMU\n"); 277 break; 278 279 default: 280 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 281 break; 282 } 283 284 #ifdef CONFIG_TARGET_LS1088AQDS 285 printf("FPGA: v%d (%s), build %d", 286 (int)QIXIS_READ(scver), qixis_read_tag(buf), 287 (int)qixis_read_minor()); 288 /* the timestamp string contains "\n" at the end */ 289 printf(" on %s", qixis_read_time(buf)); 290 #else 291 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); 292 #endif 293 294 /* 295 * Display the actual SERDES reference clocks as configured by the 296 * dip switches on the board. Note that the SWx registers could 297 * technically be set to force the reference clocks to match the 298 * values that the SERDES expects (or vice versa). For now, however, 299 * we just display both values and hope the user notices when they 300 * don't match. 301 */ 302 puts("SERDES1 Reference : "); 303 sw = QIXIS_READ(brdcfg[2]); 304 clock = (sw >> 6) & 3; 305 printf("Clock1 = %sMHz ", freq[clock]); 306 clock = (sw >> 4) & 3; 307 printf("Clock2 = %sMHz", freq[clock]); 308 309 puts("\nSERDES2 Reference : "); 310 clock = (sw >> 2) & 3; 311 printf("Clock1 = %sMHz ", freq[clock]); 312 clock = (sw >> 0) & 3; 313 printf("Clock2 = %sMHz\n", freq[clock]); 314 315 return 0; 316 } 317 #endif 318 319 bool if_board_diff_clk(void) 320 { 321 #ifdef CONFIG_TARGET_LS1088AQDS 322 u8 diff_conf = QIXIS_READ(brdcfg[11]); 323 return diff_conf & 0x40; 324 #else 325 u8 diff_conf = QIXIS_READ(dutcfg[11]); 326 return diff_conf & 0x80; 327 #endif 328 } 329 330 unsigned long get_board_sys_clk(void) 331 { 332 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 333 334 switch (sysclk_conf & 0x0f) { 335 case QIXIS_SYSCLK_83: 336 return 83333333; 337 case QIXIS_SYSCLK_100: 338 return 100000000; 339 case QIXIS_SYSCLK_125: 340 return 125000000; 341 case QIXIS_SYSCLK_133: 342 return 133333333; 343 case QIXIS_SYSCLK_150: 344 return 150000000; 345 case QIXIS_SYSCLK_160: 346 return 160000000; 347 case QIXIS_SYSCLK_166: 348 return 166666666; 349 } 350 351 return 66666666; 352 } 353 354 unsigned long get_board_ddr_clk(void) 355 { 356 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 357 358 if (if_board_diff_clk()) 359 return get_board_sys_clk(); 360 switch ((ddrclk_conf & 0x30) >> 4) { 361 case QIXIS_DDRCLK_100: 362 return 100000000; 363 case QIXIS_DDRCLK_125: 364 return 125000000; 365 case QIXIS_DDRCLK_133: 366 return 133333333; 367 } 368 369 return 66666666; 370 } 371 372 int select_i2c_ch_pca9547(u8 ch) 373 { 374 int ret; 375 376 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 377 if (ret) { 378 puts("PCA: failed to select proper channel\n"); 379 return ret; 380 } 381 382 return 0; 383 } 384 385 #if !defined(CONFIG_SPL_BUILD) 386 void board_retimer_init(void) 387 { 388 u8 reg; 389 390 /* Retimer is connected to I2C1_CH5 */ 391 select_i2c_ch_pca9547(I2C_MUX_CH5); 392 393 /* Access to Control/Shared register */ 394 reg = 0x0; 395 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 396 397 /* Read device revision and ID */ 398 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); 399 debug("Retimer version id = 0x%x\n", reg); 400 401 /* Enable Broadcast. All writes target all channel register sets */ 402 reg = 0x0c; 403 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 404 405 /* Reset Channel Registers */ 406 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); 407 reg |= 0x4; 408 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); 409 410 /* Set data rate as 10.3125 Gbps */ 411 reg = 0x90; 412 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); 413 reg = 0xb3; 414 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); 415 reg = 0x90; 416 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); 417 reg = 0xb3; 418 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); 419 reg = 0xcd; 420 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); 421 422 /* Select VCO Divider to full rate (000) */ 423 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); 424 reg &= 0x0f; 425 reg |= 0x70; 426 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); 427 428 #ifdef CONFIG_TARGET_LS1088AQDS 429 /* Retimer is connected to I2C1_CH5 */ 430 select_i2c_ch_pca9547(I2C_MUX_CH5); 431 432 /* Access to Control/Shared register */ 433 reg = 0x0; 434 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); 435 436 /* Read device revision and ID */ 437 i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1); 438 debug("Retimer version id = 0x%x\n", reg); 439 440 /* Enable Broadcast. All writes target all channel register sets */ 441 reg = 0x0c; 442 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); 443 444 /* Reset Channel Registers */ 445 i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1); 446 reg |= 0x4; 447 i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1); 448 449 /* Set data rate as 10.3125 Gbps */ 450 reg = 0x90; 451 i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1); 452 reg = 0xb3; 453 i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1); 454 reg = 0x90; 455 i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1); 456 reg = 0xb3; 457 i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1); 458 reg = 0xcd; 459 i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1); 460 461 /* Select VCO Divider to full rate (000) */ 462 i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); 463 reg &= 0x0f; 464 reg |= 0x70; 465 i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); 466 #endif 467 /*return the default channel*/ 468 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 469 } 470 471 #ifdef CONFIG_MISC_INIT_R 472 int misc_init_r(void) 473 { 474 #ifdef CONFIG_TARGET_LS1088ARDB 475 u8 brdcfg5; 476 477 if (hwconfig("esdhc-force-sd")) { 478 brdcfg5 = QIXIS_READ(brdcfg[5]); 479 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK; 480 brdcfg5 |= BRDCFG5_FORCE_SD; 481 QIXIS_WRITE(brdcfg[5], brdcfg5); 482 } 483 #endif 484 return 0; 485 } 486 #endif 487 #endif 488 489 int i2c_multiplexer_select_vid_channel(u8 channel) 490 { 491 return select_i2c_ch_pca9547(channel); 492 } 493 494 #ifdef CONFIG_TARGET_LS1088AQDS 495 /* read the current value(SVDD) of the LTM Regulator Voltage */ 496 int get_serdes_volt(void) 497 { 498 int ret, vcode = 0; 499 u8 chan = PWM_CHANNEL0; 500 501 /* Select the PAGE 0 using PMBus commands PAGE for VDD */ 502 ret = i2c_write(I2C_SVDD_MONITOR_ADDR, 503 PMBUS_CMD_PAGE, 1, &chan, 1); 504 if (ret) { 505 printf("VID: failed to select VDD Page 0\n"); 506 return ret; 507 } 508 509 /* Read the output voltage using PMBus command READ_VOUT */ 510 ret = i2c_read(I2C_SVDD_MONITOR_ADDR, 511 PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); 512 if (ret) { 513 printf("VID: failed to read the volatge\n"); 514 return ret; 515 } 516 517 return vcode; 518 } 519 520 int set_serdes_volt(int svdd) 521 { 522 int ret, vdd_last; 523 u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, 524 svdd & 0xFF, (svdd & 0xFF00) >> 8}; 525 526 /* Write the desired voltage code to the SVDD regulator */ 527 ret = i2c_write(I2C_SVDD_MONITOR_ADDR, 528 PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); 529 if (ret) { 530 printf("VID: I2C failed to write to the volatge regulator\n"); 531 return -1; 532 } 533 534 /* Wait for the volatge to get to the desired value */ 535 do { 536 vdd_last = get_serdes_volt(); 537 if (vdd_last < 0) { 538 printf("VID: Couldn't read sensor abort VID adjust\n"); 539 return -1; 540 } 541 } while (vdd_last != svdd); 542 543 return 1; 544 } 545 #else 546 int get_serdes_volt(void) 547 { 548 return 0; 549 } 550 551 int set_serdes_volt(int svdd) 552 { 553 int ret; 554 u8 brdcfg4; 555 556 printf("SVDD changing of RDB\n"); 557 558 /* Read the BRDCFG54 via CLPD */ 559 ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR, 560 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); 561 if (ret) { 562 printf("VID: I2C failed to read the CPLD BRDCFG4\n"); 563 return -1; 564 } 565 566 brdcfg4 = brdcfg4 | 0x08; 567 568 /* Write to the BRDCFG4 */ 569 ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 570 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); 571 if (ret) { 572 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n"); 573 return -1; 574 } 575 576 /* Wait for the volatge to get to the desired value */ 577 udelay(10000); 578 579 return 1; 580 } 581 #endif 582 583 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/ 584 int board_adjust_vdd(int vdd) 585 { 586 int ret = 0; 587 588 debug("%s: vdd = %d\n", __func__, vdd); 589 590 /* Special settings to be performed when voltage is 900mV */ 591 if (vdd == 900) { 592 ret = setup_serdes_volt(vdd); 593 if (ret < 0) { 594 ret = -1; 595 goto exit; 596 } 597 } 598 exit: 599 return ret; 600 } 601 602 #if !defined(CONFIG_SPL_BUILD) 603 int board_init(void) 604 { 605 init_final_memctl_regs(); 606 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) 607 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; 608 #endif 609 610 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 611 board_retimer_init(); 612 613 #ifdef CONFIG_ENV_IS_NOWHERE 614 gd->env_addr = (ulong)&default_environment[0]; 615 #endif 616 617 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) 618 /* invert AQR105 IRQ pins polarity */ 619 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK); 620 #endif 621 622 #ifdef CONFIG_FSL_CAAM 623 sec_init(); 624 #endif 625 #ifdef CONFIG_FSL_LS_PPA 626 ppa_init(); 627 #endif 628 return 0; 629 } 630 631 void detail_board_ddr_info(void) 632 { 633 puts("\nDDR "); 634 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); 635 print_ddr_info(0); 636 } 637 638 #if defined(CONFIG_ARCH_MISC_INIT) 639 int arch_misc_init(void) 640 { 641 return 0; 642 } 643 #endif 644 645 #ifdef CONFIG_FSL_MC_ENET 646 void board_quiesce_devices(void) 647 { 648 fsl_mc_ldpaa_exit(gd->bd); 649 } 650 651 void fdt_fixup_board_enet(void *fdt) 652 { 653 int offset; 654 655 offset = fdt_path_offset(fdt, "/fsl-mc"); 656 657 if (offset < 0) 658 offset = fdt_path_offset(fdt, "/soc/fsl-mc"); 659 660 if (offset < 0) { 661 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", 662 __func__, offset); 663 return; 664 } 665 666 if (get_mc_boot_status() == 0 && 667 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) 668 fdt_status_okay(fdt, offset); 669 else 670 fdt_status_fail(fdt, offset); 671 } 672 #endif 673 674 #ifdef CONFIG_OF_BOARD_SETUP 675 void fsl_fdt_fixup_flash(void *fdt) 676 { 677 int offset; 678 #ifdef CONFIG_TFABOOT 679 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 680 u32 val; 681 #endif 682 683 /* 684 * IFC-NOR and QSPI are muxed on SoC. 685 * So disable IFC node in dts if QSPI is enabled or 686 * disable QSPI node in dts in case QSPI is not enabled. 687 */ 688 689 #ifdef CONFIG_TFABOOT 690 enum boot_src src = get_boot_src(); 691 bool disable_ifc = false; 692 693 switch (src) { 694 case BOOT_SOURCE_IFC_NOR: 695 disable_ifc = false; 696 break; 697 case BOOT_SOURCE_QSPI_NOR: 698 disable_ifc = true; 699 break; 700 default: 701 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4); 702 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3)) 703 disable_ifc = true; 704 break; 705 } 706 707 if (disable_ifc) { 708 offset = fdt_path_offset(fdt, "/soc/ifc/nor"); 709 710 if (offset < 0) 711 offset = fdt_path_offset(fdt, "/ifc/nor"); 712 } else { 713 offset = fdt_path_offset(fdt, "/soc/quadspi"); 714 715 if (offset < 0) 716 offset = fdt_path_offset(fdt, "/quadspi"); 717 } 718 719 #else 720 #ifdef CONFIG_FSL_QSPI 721 offset = fdt_path_offset(fdt, "/soc/ifc/nor"); 722 723 if (offset < 0) 724 offset = fdt_path_offset(fdt, "/ifc/nor"); 725 #else 726 offset = fdt_path_offset(fdt, "/soc/quadspi"); 727 728 if (offset < 0) 729 offset = fdt_path_offset(fdt, "/quadspi"); 730 #endif 731 #endif 732 if (offset < 0) 733 return; 734 735 fdt_status_disabled(fdt, offset); 736 } 737 738 int ft_board_setup(void *blob, bd_t *bd) 739 { 740 int i; 741 u64 base[CONFIG_NR_DRAM_BANKS]; 742 u64 size[CONFIG_NR_DRAM_BANKS]; 743 744 ft_cpu_setup(blob, bd); 745 746 /* fixup DT for the two GPP DDR banks */ 747 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 748 base[i] = gd->bd->bi_dram[i].start; 749 size[i] = gd->bd->bi_dram[i].size; 750 } 751 752 #ifdef CONFIG_RESV_RAM 753 /* reduce size if reserved memory is within this bank */ 754 if (gd->arch.resv_ram >= base[0] && 755 gd->arch.resv_ram < base[0] + size[0]) 756 size[0] = gd->arch.resv_ram - base[0]; 757 else if (gd->arch.resv_ram >= base[1] && 758 gd->arch.resv_ram < base[1] + size[1]) 759 size[1] = gd->arch.resv_ram - base[1]; 760 #endif 761 762 fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); 763 764 fdt_fsl_mc_fixup_iommu_map_entry(blob); 765 766 fsl_fdt_fixup_flash(blob); 767 768 #ifdef CONFIG_FSL_MC_ENET 769 fdt_fixup_board_enet(blob); 770 #endif 771 if (is_pb_board()) 772 fixup_ls1088ardb_pb_banner(blob); 773 774 return 0; 775 } 776 #endif 777 #endif /* defined(CONFIG_SPL_BUILD) */ 778 779 #ifdef CONFIG_TFABOOT 780 #ifdef CONFIG_MTD_NOR_FLASH 781 int is_flash_available(void) 782 { 783 char *env_hwconfig = env_get("hwconfig"); 784 enum boot_src src = get_boot_src(); 785 int is_nor_flash_available = 1; 786 787 switch (src) { 788 case BOOT_SOURCE_IFC_NOR: 789 is_nor_flash_available = 1; 790 break; 791 case BOOT_SOURCE_QSPI_NOR: 792 is_nor_flash_available = 0; 793 break; 794 /* 795 * In Case of SD boot,if qspi is defined in env_hwconfig 796 * disable nor flash probe. 797 */ 798 default: 799 if (hwconfig_f("qspi", env_hwconfig)) 800 is_nor_flash_available = 0; 801 break; 802 } 803 return is_nor_flash_available; 804 } 805 #endif 806 807 void *env_sf_get_env_addr(void) 808 { 809 return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); 810 } 811 #endif 812