1 /* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <i2c.h> 8 #include <malloc.h> 9 #include <errno.h> 10 #include <netdev.h> 11 #include <fsl_ifc.h> 12 #include <fsl_ddr.h> 13 #include <fsl_sec.h> 14 #include <asm/io.h> 15 #include <fdt_support.h> 16 #include <linux/libfdt.h> 17 #include <fsl-mc/fsl_mc.h> 18 #include <environment.h> 19 #include <asm/arch-fsl-layerscape/soc.h> 20 #include <asm/arch/ppa.h> 21 #include <hwconfig.h> 22 #include <asm/arch/fsl_serdes.h> 23 #include <asm/arch/soc.h> 24 25 #include "../common/qixis.h" 26 #include "ls1088a_qixis.h" 27 #include "../common/vid.h" 28 #include <fsl_immap.h> 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 int board_early_init_f(void) 33 { 34 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS) 35 i2c_early_init_f(); 36 #endif 37 fsl_lsch3_early_init_f(); 38 return 0; 39 } 40 41 #ifdef CONFIG_FSL_QIXIS 42 unsigned long long get_qixis_addr(void) 43 { 44 unsigned long long addr; 45 46 if (gd->flags & GD_FLG_RELOC) 47 addr = QIXIS_BASE_PHYS; 48 else 49 addr = QIXIS_BASE_PHYS_EARLY; 50 51 /* 52 * IFC address under 256MB is mapped to 0x30000000, any address above 53 * is mapped to 0x5_10000000 up to 4GB. 54 */ 55 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; 56 57 return addr; 58 } 59 #endif 60 61 #if defined(CONFIG_VID) 62 int init_func_vid(void) 63 { 64 if (adjust_vdd(0) < 0) 65 printf("core voltage not adjusted\n"); 66 67 return 0; 68 } 69 #endif 70 71 #if !defined(CONFIG_SPL_BUILD) 72 int checkboard(void) 73 { 74 char buf[64]; 75 u8 sw; 76 static const char *const freq[] = {"100", "125", "156.25", 77 "100 separate SSCG"}; 78 int clock; 79 80 #ifdef CONFIG_TARGET_LS1088AQDS 81 printf("Board: LS1088A-QDS, "); 82 #else 83 printf("Board: LS1088A-RDB, "); 84 #endif 85 86 sw = QIXIS_READ(arch); 87 printf("Board Arch: V%d, ", sw >> 4); 88 89 #ifdef CONFIG_TARGET_LS1088AQDS 90 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); 91 #else 92 printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); 93 #endif 94 95 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); 96 97 sw = QIXIS_READ(brdcfg[0]); 98 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 99 100 #ifdef CONFIG_SD_BOOT 101 puts("SD card\n"); 102 #endif 103 switch (sw) { 104 #ifdef CONFIG_TARGET_LS1088AQDS 105 case 0: 106 case 1: 107 case 2: 108 case 3: 109 case 4: 110 case 5: 111 case 6: 112 case 7: 113 printf("vBank: %d\n", sw); 114 break; 115 case 8: 116 puts("PromJet\n"); 117 break; 118 case 15: 119 puts("IFCCard\n"); 120 break; 121 case 14: 122 #else 123 case 0: 124 #endif 125 puts("QSPI:"); 126 sw = QIXIS_READ(brdcfg[0]); 127 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT; 128 if (sw == 0 || sw == 4) 129 puts("0\n"); 130 else if (sw == 1) 131 puts("1\n"); 132 else 133 puts("EMU\n"); 134 break; 135 136 default: 137 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 138 break; 139 } 140 141 #ifdef CONFIG_TARGET_LS1088AQDS 142 printf("FPGA: v%d (%s), build %d", 143 (int)QIXIS_READ(scver), qixis_read_tag(buf), 144 (int)qixis_read_minor()); 145 /* the timestamp string contains "\n" at the end */ 146 printf(" on %s", qixis_read_time(buf)); 147 #else 148 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); 149 #endif 150 151 /* 152 * Display the actual SERDES reference clocks as configured by the 153 * dip switches on the board. Note that the SWx registers could 154 * technically be set to force the reference clocks to match the 155 * values that the SERDES expects (or vice versa). For now, however, 156 * we just display both values and hope the user notices when they 157 * don't match. 158 */ 159 puts("SERDES1 Reference : "); 160 sw = QIXIS_READ(brdcfg[2]); 161 clock = (sw >> 6) & 3; 162 printf("Clock1 = %sMHz ", freq[clock]); 163 clock = (sw >> 4) & 3; 164 printf("Clock2 = %sMHz", freq[clock]); 165 166 puts("\nSERDES2 Reference : "); 167 clock = (sw >> 2) & 3; 168 printf("Clock1 = %sMHz ", freq[clock]); 169 clock = (sw >> 0) & 3; 170 printf("Clock2 = %sMHz\n", freq[clock]); 171 172 return 0; 173 } 174 #endif 175 176 bool if_board_diff_clk(void) 177 { 178 #ifdef CONFIG_TARGET_LS1088AQDS 179 u8 diff_conf = QIXIS_READ(brdcfg[11]); 180 return diff_conf & 0x40; 181 #else 182 u8 diff_conf = QIXIS_READ(dutcfg[11]); 183 return diff_conf & 0x80; 184 #endif 185 } 186 187 unsigned long get_board_sys_clk(void) 188 { 189 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 190 191 switch (sysclk_conf & 0x0f) { 192 case QIXIS_SYSCLK_83: 193 return 83333333; 194 case QIXIS_SYSCLK_100: 195 return 100000000; 196 case QIXIS_SYSCLK_125: 197 return 125000000; 198 case QIXIS_SYSCLK_133: 199 return 133333333; 200 case QIXIS_SYSCLK_150: 201 return 150000000; 202 case QIXIS_SYSCLK_160: 203 return 160000000; 204 case QIXIS_SYSCLK_166: 205 return 166666666; 206 } 207 208 return 66666666; 209 } 210 211 unsigned long get_board_ddr_clk(void) 212 { 213 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 214 215 if (if_board_diff_clk()) 216 return get_board_sys_clk(); 217 switch ((ddrclk_conf & 0x30) >> 4) { 218 case QIXIS_DDRCLK_100: 219 return 100000000; 220 case QIXIS_DDRCLK_125: 221 return 125000000; 222 case QIXIS_DDRCLK_133: 223 return 133333333; 224 } 225 226 return 66666666; 227 } 228 229 int select_i2c_ch_pca9547(u8 ch) 230 { 231 int ret; 232 233 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 234 if (ret) { 235 puts("PCA: failed to select proper channel\n"); 236 return ret; 237 } 238 239 return 0; 240 } 241 242 #if !defined(CONFIG_SPL_BUILD) 243 void board_retimer_init(void) 244 { 245 u8 reg; 246 247 /* Retimer is connected to I2C1_CH5 */ 248 select_i2c_ch_pca9547(I2C_MUX_CH5); 249 250 /* Access to Control/Shared register */ 251 reg = 0x0; 252 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 253 254 /* Read device revision and ID */ 255 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); 256 debug("Retimer version id = 0x%x\n", reg); 257 258 /* Enable Broadcast. All writes target all channel register sets */ 259 reg = 0x0c; 260 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 261 262 /* Reset Channel Registers */ 263 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); 264 reg |= 0x4; 265 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); 266 267 /* Set data rate as 10.3125 Gbps */ 268 reg = 0x90; 269 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); 270 reg = 0xb3; 271 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); 272 reg = 0x90; 273 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); 274 reg = 0xb3; 275 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); 276 reg = 0xcd; 277 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); 278 279 /* Select VCO Divider to full rate (000) */ 280 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); 281 reg &= 0x0f; 282 reg |= 0x70; 283 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); 284 285 #ifdef CONFIG_TARGET_LS1088AQDS 286 /* Retimer is connected to I2C1_CH5 */ 287 select_i2c_ch_pca9547(I2C_MUX_CH5); 288 289 /* Access to Control/Shared register */ 290 reg = 0x0; 291 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); 292 293 /* Read device revision and ID */ 294 i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1); 295 debug("Retimer version id = 0x%x\n", reg); 296 297 /* Enable Broadcast. All writes target all channel register sets */ 298 reg = 0x0c; 299 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); 300 301 /* Reset Channel Registers */ 302 i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1); 303 reg |= 0x4; 304 i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1); 305 306 /* Set data rate as 10.3125 Gbps */ 307 reg = 0x90; 308 i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1); 309 reg = 0xb3; 310 i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1); 311 reg = 0x90; 312 i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1); 313 reg = 0xb3; 314 i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1); 315 reg = 0xcd; 316 i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1); 317 318 /* Select VCO Divider to full rate (000) */ 319 i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); 320 reg &= 0x0f; 321 reg |= 0x70; 322 i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); 323 #endif 324 /*return the default channel*/ 325 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 326 } 327 328 #ifdef CONFIG_MISC_INIT_R 329 int misc_init_r(void) 330 { 331 #ifdef CONFIG_TARGET_LS1088ARDB 332 u8 brdcfg5; 333 334 if (hwconfig("esdhc-force-sd")) { 335 brdcfg5 = QIXIS_READ(brdcfg[5]); 336 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK; 337 brdcfg5 |= BRDCFG5_FORCE_SD; 338 QIXIS_WRITE(brdcfg[5], brdcfg5); 339 } 340 #endif 341 return 0; 342 } 343 #endif 344 #endif 345 346 int i2c_multiplexer_select_vid_channel(u8 channel) 347 { 348 return select_i2c_ch_pca9547(channel); 349 } 350 351 #ifdef CONFIG_TARGET_LS1088AQDS 352 /* read the current value(SVDD) of the LTM Regulator Voltage */ 353 int get_serdes_volt(void) 354 { 355 int ret, vcode = 0; 356 u8 chan = PWM_CHANNEL0; 357 358 /* Select the PAGE 0 using PMBus commands PAGE for VDD */ 359 ret = i2c_write(I2C_SVDD_MONITOR_ADDR, 360 PMBUS_CMD_PAGE, 1, &chan, 1); 361 if (ret) { 362 printf("VID: failed to select VDD Page 0\n"); 363 return ret; 364 } 365 366 /* Read the output voltage using PMBus command READ_VOUT */ 367 ret = i2c_read(I2C_SVDD_MONITOR_ADDR, 368 PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); 369 if (ret) { 370 printf("VID: failed to read the volatge\n"); 371 return ret; 372 } 373 374 return vcode; 375 } 376 377 int set_serdes_volt(int svdd) 378 { 379 int ret, vdd_last; 380 u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, 381 svdd & 0xFF, (svdd & 0xFF00) >> 8}; 382 383 /* Write the desired voltage code to the SVDD regulator */ 384 ret = i2c_write(I2C_SVDD_MONITOR_ADDR, 385 PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); 386 if (ret) { 387 printf("VID: I2C failed to write to the volatge regulator\n"); 388 return -1; 389 } 390 391 /* Wait for the volatge to get to the desired value */ 392 do { 393 vdd_last = get_serdes_volt(); 394 if (vdd_last < 0) { 395 printf("VID: Couldn't read sensor abort VID adjust\n"); 396 return -1; 397 } 398 } while (vdd_last != svdd); 399 400 return 1; 401 } 402 #else 403 int get_serdes_volt(void) 404 { 405 return 0; 406 } 407 408 int set_serdes_volt(int svdd) 409 { 410 int ret; 411 u8 brdcfg4; 412 413 printf("SVDD changing of RDB\n"); 414 415 /* Read the BRDCFG54 via CLPD */ 416 ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR, 417 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); 418 if (ret) { 419 printf("VID: I2C failed to read the CPLD BRDCFG4\n"); 420 return -1; 421 } 422 423 brdcfg4 = brdcfg4 | 0x08; 424 425 /* Write to the BRDCFG4 */ 426 ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 427 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); 428 if (ret) { 429 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n"); 430 return -1; 431 } 432 433 /* Wait for the volatge to get to the desired value */ 434 udelay(10000); 435 436 return 1; 437 } 438 #endif 439 440 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/ 441 int board_adjust_vdd(int vdd) 442 { 443 int ret = 0; 444 445 debug("%s: vdd = %d\n", __func__, vdd); 446 447 /* Special settings to be performed when voltage is 900mV */ 448 if (vdd == 900) { 449 ret = setup_serdes_volt(vdd); 450 if (ret < 0) { 451 ret = -1; 452 goto exit; 453 } 454 } 455 exit: 456 return ret; 457 } 458 459 #if !defined(CONFIG_SPL_BUILD) 460 int board_init(void) 461 { 462 init_final_memctl_regs(); 463 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) 464 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; 465 #endif 466 467 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 468 board_retimer_init(); 469 470 #ifdef CONFIG_ENV_IS_NOWHERE 471 gd->env_addr = (ulong)&default_environment[0]; 472 #endif 473 474 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) 475 /* invert AQR105 IRQ pins polarity */ 476 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK); 477 #endif 478 479 #ifdef CONFIG_FSL_CAAM 480 sec_init(); 481 #endif 482 #ifdef CONFIG_FSL_LS_PPA 483 ppa_init(); 484 #endif 485 return 0; 486 } 487 488 void detail_board_ddr_info(void) 489 { 490 puts("\nDDR "); 491 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); 492 print_ddr_info(0); 493 } 494 495 #if defined(CONFIG_ARCH_MISC_INIT) 496 int arch_misc_init(void) 497 { 498 return 0; 499 } 500 #endif 501 502 #ifdef CONFIG_FSL_MC_ENET 503 void fdt_fixup_board_enet(void *fdt) 504 { 505 int offset; 506 507 offset = fdt_path_offset(fdt, "/fsl-mc"); 508 509 if (offset < 0) 510 offset = fdt_path_offset(fdt, "/fsl,dprc@0"); 511 512 if (offset < 0) { 513 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", 514 __func__, offset); 515 return; 516 } 517 518 if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) 519 fdt_status_okay(fdt, offset); 520 else 521 fdt_status_fail(fdt, offset); 522 } 523 #endif 524 525 #ifdef CONFIG_OF_BOARD_SETUP 526 void fsl_fdt_fixup_flash(void *fdt) 527 { 528 int offset; 529 530 /* 531 * IFC-NOR and QSPI are muxed on SoC. 532 * So disable IFC node in dts if QSPI is enabled or 533 * disable QSPI node in dts in case QSPI is not enabled. 534 */ 535 536 #ifdef CONFIG_FSL_QSPI 537 offset = fdt_path_offset(fdt, "/soc/ifc/nor"); 538 539 if (offset < 0) 540 offset = fdt_path_offset(fdt, "/ifc/nor"); 541 #else 542 offset = fdt_path_offset(fdt, "/soc/quadspi"); 543 544 if (offset < 0) 545 offset = fdt_path_offset(fdt, "/quadspi"); 546 #endif 547 if (offset < 0) 548 return; 549 550 fdt_status_disabled(fdt, offset); 551 } 552 553 int ft_board_setup(void *blob, bd_t *bd) 554 { 555 int err, i; 556 u64 base[CONFIG_NR_DRAM_BANKS]; 557 u64 size[CONFIG_NR_DRAM_BANKS]; 558 559 ft_cpu_setup(blob, bd); 560 561 /* fixup DT for the two GPP DDR banks */ 562 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 563 base[i] = gd->bd->bi_dram[i].start; 564 size[i] = gd->bd->bi_dram[i].size; 565 } 566 567 #ifdef CONFIG_RESV_RAM 568 /* reduce size if reserved memory is within this bank */ 569 if (gd->arch.resv_ram >= base[0] && 570 gd->arch.resv_ram < base[0] + size[0]) 571 size[0] = gd->arch.resv_ram - base[0]; 572 else if (gd->arch.resv_ram >= base[1] && 573 gd->arch.resv_ram < base[1] + size[1]) 574 size[1] = gd->arch.resv_ram - base[1]; 575 #endif 576 577 fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); 578 579 fsl_fdt_fixup_flash(blob); 580 581 #ifdef CONFIG_FSL_MC_ENET 582 fdt_fixup_board_enet(blob); 583 err = fsl_mc_ldpaa_exit(bd); 584 if (err) 585 return err; 586 #endif 587 588 return 0; 589 } 590 #endif 591 #endif /* defined(CONFIG_SPL_BUILD) */ 592