1 /*
2  * Copyright 2017 NXP
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 #include <common.h>
7 #include <i2c.h>
8 #include <malloc.h>
9 #include <errno.h>
10 #include <netdev.h>
11 #include <fsl_ifc.h>
12 #include <fsl_ddr.h>
13 #include <fsl_sec.h>
14 #include <asm/io.h>
15 #include <fdt_support.h>
16 #include <linux/libfdt.h>
17 #include <fsl-mc/fsl_mc.h>
18 #include <environment.h>
19 #include <asm/arch-fsl-layerscape/soc.h>
20 #include <asm/arch/ppa.h>
21 #include <hwconfig.h>
22 #include <asm/arch/fsl_serdes.h>
23 #include <asm/arch/soc.h>
24 
25 #include "../common/qixis.h"
26 #include "ls1088a_qixis.h"
27 #include "../common/vid.h"
28 #include <fsl_immap.h>
29 
30 DECLARE_GLOBAL_DATA_PTR;
31 
32 int board_early_init_f(void)
33 {
34 	fsl_lsch3_early_init_f();
35 	return 0;
36 }
37 
38 #ifdef CONFIG_FSL_QIXIS
39 unsigned long long get_qixis_addr(void)
40 {
41 	unsigned long long addr;
42 
43 	if (gd->flags & GD_FLG_RELOC)
44 		addr = QIXIS_BASE_PHYS;
45 	else
46 		addr = QIXIS_BASE_PHYS_EARLY;
47 
48 	/*
49 	 * IFC address under 256MB is mapped to 0x30000000, any address above
50 	 * is mapped to 0x5_10000000 up to 4GB.
51 	 */
52 	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
53 
54 	return addr;
55 }
56 #endif
57 
58 #if defined(CONFIG_VID)
59 int init_func_vid(void)
60 {
61 	if (adjust_vdd(0) < 0)
62 		printf("core voltage not adjusted\n");
63 
64 	return 0;
65 }
66 #endif
67 
68 #if !defined(CONFIG_SPL_BUILD)
69 int checkboard(void)
70 {
71 	char buf[64];
72 	u8 sw;
73 	static const char *const freq[] = {"100", "125", "156.25",
74 					    "100 separate SSCG"};
75 	int clock;
76 
77 #ifdef CONFIG_TARGET_LS1088AQDS
78 	printf("Board: LS1088A-QDS, ");
79 #else
80 	printf("Board: LS1088A-RDB, ");
81 #endif
82 
83 	sw = QIXIS_READ(arch);
84 	printf("Board Arch: V%d, ", sw >> 4);
85 
86 #ifdef CONFIG_TARGET_LS1088AQDS
87 	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
88 #else
89 	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
90 #endif
91 
92 	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
93 
94 	sw = QIXIS_READ(brdcfg[0]);
95 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
96 
97 #ifdef CONFIG_SD_BOOT
98 	puts("SD card\n");
99 #endif
100 	switch (sw) {
101 #ifdef CONFIG_TARGET_LS1088AQDS
102 	case 0:
103 	case 1:
104 	case 2:
105 	case 3:
106 	case 4:
107 	case 5:
108 	case 6:
109 	case 7:
110 		printf("vBank: %d\n", sw);
111 		break;
112 	case 8:
113 		puts("PromJet\n");
114 		break;
115 	case 15:
116 		puts("IFCCard\n");
117 		break;
118 	case 14:
119 #else
120 	case 0:
121 #endif
122 		puts("QSPI:");
123 		sw = QIXIS_READ(brdcfg[0]);
124 		sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
125 		if (sw == 0 || sw == 4)
126 			puts("0\n");
127 		else if (sw == 1)
128 			puts("1\n");
129 		else
130 			puts("EMU\n");
131 		break;
132 
133 	default:
134 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
135 		break;
136 	}
137 
138 #ifdef CONFIG_TARGET_LS1088AQDS
139 	printf("FPGA: v%d (%s), build %d",
140 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
141 	       (int)qixis_read_minor());
142 	/* the timestamp string contains "\n" at the end */
143 	printf(" on %s", qixis_read_time(buf));
144 #else
145 	printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
146 #endif
147 
148 	/*
149 	 * Display the actual SERDES reference clocks as configured by the
150 	 * dip switches on the board.  Note that the SWx registers could
151 	 * technically be set to force the reference clocks to match the
152 	 * values that the SERDES expects (or vice versa).  For now, however,
153 	 * we just display both values and hope the user notices when they
154 	 * don't match.
155 	 */
156 	puts("SERDES1 Reference : ");
157 	sw = QIXIS_READ(brdcfg[2]);
158 	clock = (sw >> 6) & 3;
159 	printf("Clock1 = %sMHz ", freq[clock]);
160 	clock = (sw >> 4) & 3;
161 	printf("Clock2 = %sMHz", freq[clock]);
162 
163 	puts("\nSERDES2 Reference : ");
164 	clock = (sw >> 2) & 3;
165 	printf("Clock1 = %sMHz ", freq[clock]);
166 	clock = (sw >> 0) & 3;
167 	printf("Clock2 = %sMHz\n", freq[clock]);
168 
169 	return 0;
170 }
171 
172 bool if_board_diff_clk(void)
173 {
174 #ifdef CONFIG_TARGET_LS1088AQDS
175 	u8 diff_conf = QIXIS_READ(brdcfg[11]);
176 	return diff_conf & 0x40;
177 #else
178 	u8 diff_conf = QIXIS_READ(dutcfg[11]);
179 	return diff_conf & 0x80;
180 #endif
181 }
182 
183 unsigned long get_board_sys_clk(void)
184 {
185 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
186 
187 	switch (sysclk_conf & 0x0f) {
188 	case QIXIS_SYSCLK_83:
189 		return 83333333;
190 	case QIXIS_SYSCLK_100:
191 		return 100000000;
192 	case QIXIS_SYSCLK_125:
193 		return 125000000;
194 	case QIXIS_SYSCLK_133:
195 		return 133333333;
196 	case QIXIS_SYSCLK_150:
197 		return 150000000;
198 	case QIXIS_SYSCLK_160:
199 		return 160000000;
200 	case QIXIS_SYSCLK_166:
201 		return 166666666;
202 	}
203 
204 	return 66666666;
205 }
206 
207 unsigned long get_board_ddr_clk(void)
208 {
209 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
210 
211 	if (if_board_diff_clk())
212 		return get_board_sys_clk();
213 	switch ((ddrclk_conf & 0x30) >> 4) {
214 	case QIXIS_DDRCLK_100:
215 		return 100000000;
216 	case QIXIS_DDRCLK_125:
217 		return 125000000;
218 	case QIXIS_DDRCLK_133:
219 		return 133333333;
220 	}
221 
222 	return 66666666;
223 }
224 #endif
225 
226 int select_i2c_ch_pca9547(u8 ch)
227 {
228 	int ret;
229 
230 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
231 	if (ret) {
232 		puts("PCA: failed to select proper channel\n");
233 		return ret;
234 	}
235 
236 	return 0;
237 }
238 
239 #if !defined(CONFIG_SPL_BUILD)
240 void board_retimer_init(void)
241 {
242 	u8 reg;
243 
244 	/* Retimer is connected to I2C1_CH5 */
245 	select_i2c_ch_pca9547(I2C_MUX_CH5);
246 
247 	/* Access to Control/Shared register */
248 	reg = 0x0;
249 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
250 
251 	/* Read device revision and ID */
252 	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
253 	debug("Retimer version id = 0x%x\n", reg);
254 
255 	/* Enable Broadcast. All writes target all channel register sets */
256 	reg = 0x0c;
257 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
258 
259 	/* Reset Channel Registers */
260 	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
261 	reg |= 0x4;
262 	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
263 
264 	/* Set data rate as 10.3125 Gbps */
265 	reg = 0x90;
266 	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
267 	reg = 0xb3;
268 	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
269 	reg = 0x90;
270 	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
271 	reg = 0xb3;
272 	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
273 	reg = 0xcd;
274 	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
275 
276 	/* Select VCO Divider to full rate (000) */
277 	i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
278 	reg &= 0x0f;
279 	reg |= 0x70;
280 	i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
281 
282 #ifdef	CONFIG_TARGET_LS1088AQDS
283 	/* Retimer is connected to I2C1_CH5 */
284 	select_i2c_ch_pca9547(I2C_MUX_CH5);
285 
286 	/* Access to Control/Shared register */
287 	reg = 0x0;
288 	i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
289 
290 	/* Read device revision and ID */
291 	i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
292 	debug("Retimer version id = 0x%x\n", reg);
293 
294 	/* Enable Broadcast. All writes target all channel register sets */
295 	reg = 0x0c;
296 	i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
297 
298 	/* Reset Channel Registers */
299 	i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
300 	reg |= 0x4;
301 	i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
302 
303 	/* Set data rate as 10.3125 Gbps */
304 	reg = 0x90;
305 	i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
306 	reg = 0xb3;
307 	i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
308 	reg = 0x90;
309 	i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
310 	reg = 0xb3;
311 	i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
312 	reg = 0xcd;
313 	i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
314 
315 	/* Select VCO Divider to full rate (000) */
316 	i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
317 	reg &= 0x0f;
318 	reg |= 0x70;
319 	i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
320 #endif
321 	/*return the default channel*/
322 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
323 }
324 
325 #ifdef CONFIG_MISC_INIT_R
326 int misc_init_r(void)
327 {
328 #ifdef CONFIG_TARGET_LS1088ARDB
329 	u8 brdcfg5;
330 
331 	if (hwconfig("esdhc-force-sd")) {
332 		brdcfg5 = QIXIS_READ(brdcfg[5]);
333 		brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
334 		brdcfg5 |= BRDCFG5_FORCE_SD;
335 		QIXIS_WRITE(brdcfg[5], brdcfg5);
336 	}
337 #endif
338 	return 0;
339 }
340 #endif
341 #endif
342 
343 int i2c_multiplexer_select_vid_channel(u8 channel)
344 {
345 	return select_i2c_ch_pca9547(channel);
346 }
347 
348 #ifdef CONFIG_TARGET_LS1088AQDS
349 /* read the current value(SVDD) of the LTM Regulator Voltage */
350 int get_serdes_volt(void)
351 {
352 	int  ret, vcode = 0;
353 	u8 chan = PWM_CHANNEL0;
354 
355 	/* Select the PAGE 0 using PMBus commands PAGE for VDD */
356 	ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
357 			PMBUS_CMD_PAGE, 1, &chan, 1);
358 	if (ret) {
359 		printf("VID: failed to select VDD Page 0\n");
360 		return ret;
361 	}
362 
363 	/* Read the output voltage using PMBus command READ_VOUT */
364 	ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
365 		       PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
366 	if (ret) {
367 		printf("VID: failed to read the volatge\n");
368 		return ret;
369 	}
370 
371 	return vcode;
372 }
373 
374 int set_serdes_volt(int svdd)
375 {
376 	int ret, vdd_last;
377 	u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
378 			svdd & 0xFF, (svdd & 0xFF00) >> 8};
379 
380 	/* Write the desired voltage code to the SVDD regulator */
381 	ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
382 			PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
383 	if (ret) {
384 		printf("VID: I2C failed to write to the volatge regulator\n");
385 		return -1;
386 	}
387 
388 	/* Wait for the volatge to get to the desired value */
389 	do {
390 		vdd_last = get_serdes_volt();
391 		if (vdd_last < 0) {
392 			printf("VID: Couldn't read sensor abort VID adjust\n");
393 			return -1;
394 		}
395 	} while (vdd_last != svdd);
396 
397 	return 1;
398 }
399 #else
400 int get_serdes_volt(void)
401 {
402 	return 0;
403 }
404 
405 int set_serdes_volt(int svdd)
406 {
407 	int ret;
408 	u8 brdcfg4;
409 
410 	printf("SVDD changing of RDB\n");
411 
412 	/* Read the BRDCFG54 via CLPD */
413 	ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
414 		       QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
415 	if (ret) {
416 		printf("VID: I2C failed to read the CPLD BRDCFG4\n");
417 		return -1;
418 	}
419 
420 	brdcfg4 = brdcfg4 | 0x08;
421 
422 	/* Write to the BRDCFG4 */
423 	ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
424 			QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
425 	if (ret) {
426 		debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
427 		return -1;
428 	}
429 
430 	/* Wait for the volatge to get to the desired value */
431 	udelay(10000);
432 
433 	return 1;
434 }
435 #endif
436 
437 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
438 int board_adjust_vdd(int vdd)
439 {
440 	int ret = 0;
441 
442 	debug("%s: vdd = %d\n", __func__, vdd);
443 
444 	/* Special settings to be performed when voltage is 900mV */
445 	if (vdd == 900) {
446 		ret = setup_serdes_volt(vdd);
447 		if (ret < 0) {
448 			ret = -1;
449 			goto exit;
450 		}
451 	}
452 exit:
453 	return ret;
454 }
455 
456 #if !defined(CONFIG_SPL_BUILD)
457 int board_init(void)
458 {
459 	init_final_memctl_regs();
460 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
461 	u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
462 #endif
463 
464 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
465 	board_retimer_init();
466 
467 #ifdef CONFIG_ENV_IS_NOWHERE
468 	gd->env_addr = (ulong)&default_environment[0];
469 #endif
470 
471 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
472 	/* invert AQR105 IRQ pins polarity */
473 	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
474 #endif
475 
476 #ifdef CONFIG_FSL_CAAM
477 	sec_init();
478 #endif
479 #ifdef CONFIG_FSL_LS_PPA
480 	ppa_init();
481 #endif
482 	return 0;
483 }
484 
485 void detail_board_ddr_info(void)
486 {
487 	puts("\nDDR    ");
488 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
489 	print_ddr_info(0);
490 }
491 
492 #if defined(CONFIG_ARCH_MISC_INIT)
493 int arch_misc_init(void)
494 {
495 	return 0;
496 }
497 #endif
498 
499 #ifdef CONFIG_FSL_MC_ENET
500 void fdt_fixup_board_enet(void *fdt)
501 {
502 	int offset;
503 
504 	offset = fdt_path_offset(fdt, "/fsl-mc");
505 
506 	if (offset < 0)
507 		offset = fdt_path_offset(fdt, "/fsl,dprc@0");
508 
509 	if (offset < 0) {
510 		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
511 		       __func__, offset);
512 		return;
513 	}
514 
515 	if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
516 		fdt_status_okay(fdt, offset);
517 	else
518 		fdt_status_fail(fdt, offset);
519 }
520 #endif
521 
522 #ifdef CONFIG_OF_BOARD_SETUP
523 void fsl_fdt_fixup_flash(void *fdt)
524 {
525 	int offset;
526 
527 /*
528  * IFC-NOR and QSPI are muxed on SoC.
529  * So disable IFC node in dts if QSPI is enabled or
530  * disable QSPI node in dts in case QSPI is not enabled.
531  */
532 
533 #ifdef CONFIG_FSL_QSPI
534 	offset = fdt_path_offset(fdt, "/soc/ifc/nor");
535 
536 	if (offset < 0)
537 		offset = fdt_path_offset(fdt, "/ifc/nor");
538 #else
539 	offset = fdt_path_offset(fdt, "/soc/quadspi");
540 
541 	if (offset < 0)
542 		offset = fdt_path_offset(fdt, "/quadspi");
543 #endif
544 	if (offset < 0)
545 		return;
546 
547 	fdt_status_disabled(fdt, offset);
548 }
549 
550 int ft_board_setup(void *blob, bd_t *bd)
551 {
552 	int err, i;
553 	u64 base[CONFIG_NR_DRAM_BANKS];
554 	u64 size[CONFIG_NR_DRAM_BANKS];
555 
556 	ft_cpu_setup(blob, bd);
557 
558 	/* fixup DT for the two GPP DDR banks */
559 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
560 		base[i] = gd->bd->bi_dram[i].start;
561 		size[i] = gd->bd->bi_dram[i].size;
562 	}
563 
564 #ifdef CONFIG_RESV_RAM
565 	/* reduce size if reserved memory is within this bank */
566 	if (gd->arch.resv_ram >= base[0] &&
567 	    gd->arch.resv_ram < base[0] + size[0])
568 		size[0] = gd->arch.resv_ram - base[0];
569 	else if (gd->arch.resv_ram >= base[1] &&
570 		 gd->arch.resv_ram < base[1] + size[1])
571 		size[1] = gd->arch.resv_ram - base[1];
572 #endif
573 
574 	fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
575 
576 	fsl_fdt_fixup_flash(blob);
577 
578 #ifdef CONFIG_FSL_MC_ENET
579 	fdt_fixup_board_enet(blob);
580 	err = fsl_mc_ldpaa_exit(bd);
581 	if (err)
582 		return err;
583 #endif
584 
585 	return 0;
586 }
587 #endif
588 #endif /* defined(CONFIG_SPL_BUILD) */
589