1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2017-2018 NXP 4 */ 5 #include <common.h> 6 #include <i2c.h> 7 #include <malloc.h> 8 #include <errno.h> 9 #include <netdev.h> 10 #include <fsl_ifc.h> 11 #include <fsl_ddr.h> 12 #include <fsl_sec.h> 13 #include <asm/io.h> 14 #include <fdt_support.h> 15 #include <linux/libfdt.h> 16 #include <fsl-mc/fsl_mc.h> 17 #include <environment.h> 18 #include <asm/arch-fsl-layerscape/soc.h> 19 #include <asm/arch/ppa.h> 20 #include <hwconfig.h> 21 #include <asm/arch/fsl_serdes.h> 22 #include <asm/arch/soc.h> 23 24 #include "../common/qixis.h" 25 #include "ls1088a_qixis.h" 26 #include "../common/vid.h" 27 #include <fsl_immap.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 int board_early_init_f(void) 32 { 33 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS) 34 i2c_early_init_f(); 35 #endif 36 fsl_lsch3_early_init_f(); 37 return 0; 38 } 39 40 #ifdef CONFIG_FSL_QIXIS 41 unsigned long long get_qixis_addr(void) 42 { 43 unsigned long long addr; 44 45 if (gd->flags & GD_FLG_RELOC) 46 addr = QIXIS_BASE_PHYS; 47 else 48 addr = QIXIS_BASE_PHYS_EARLY; 49 50 /* 51 * IFC address under 256MB is mapped to 0x30000000, any address above 52 * is mapped to 0x5_10000000 up to 4GB. 53 */ 54 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; 55 56 return addr; 57 } 58 #endif 59 60 #if defined(CONFIG_VID) 61 int init_func_vid(void) 62 { 63 if (adjust_vdd(0) < 0) 64 printf("core voltage not adjusted\n"); 65 66 return 0; 67 } 68 #endif 69 70 int is_pb_board(void) 71 { 72 u8 board_id; 73 74 board_id = QIXIS_READ(id); 75 if (board_id == LS1088ARDB_PB_BOARD) 76 return 1; 77 else 78 return 0; 79 } 80 81 int fixup_ls1088ardb_pb_banner(void *fdt) 82 { 83 fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board"); 84 85 return 0; 86 } 87 88 #if !defined(CONFIG_SPL_BUILD) 89 int checkboard(void) 90 { 91 #ifdef CONFIG_TFABOOT 92 enum boot_src src = get_boot_src(); 93 #endif 94 char buf[64]; 95 u8 sw; 96 static const char *const freq[] = {"100", "125", "156.25", 97 "100 separate SSCG"}; 98 int clock; 99 100 #ifdef CONFIG_TARGET_LS1088AQDS 101 printf("Board: LS1088A-QDS, "); 102 #else 103 if (is_pb_board()) 104 printf("Board: LS1088ARDB-PB, "); 105 else 106 printf("Board: LS1088A-RDB, "); 107 #endif 108 109 sw = QIXIS_READ(arch); 110 printf("Board Arch: V%d, ", sw >> 4); 111 112 #ifdef CONFIG_TARGET_LS1088AQDS 113 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); 114 #else 115 printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); 116 #endif 117 118 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); 119 120 sw = QIXIS_READ(brdcfg[0]); 121 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 122 123 #ifdef CONFIG_TFABOOT 124 if (src == BOOT_SOURCE_SD_MMC) 125 puts("SD card\n"); 126 #else 127 #ifdef CONFIG_SD_BOOT 128 puts("SD card\n"); 129 #endif 130 #endif /* CONFIG_TFABOOT */ 131 switch (sw) { 132 #ifdef CONFIG_TARGET_LS1088AQDS 133 case 0: 134 case 1: 135 case 2: 136 case 3: 137 case 4: 138 case 5: 139 case 6: 140 case 7: 141 printf("vBank: %d\n", sw); 142 break; 143 case 8: 144 puts("PromJet\n"); 145 break; 146 case 15: 147 puts("IFCCard\n"); 148 break; 149 case 14: 150 #else 151 case 0: 152 #endif 153 puts("QSPI:"); 154 sw = QIXIS_READ(brdcfg[0]); 155 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT; 156 if (sw == 0 || sw == 4) 157 puts("0\n"); 158 else if (sw == 1) 159 puts("1\n"); 160 else 161 puts("EMU\n"); 162 break; 163 164 default: 165 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 166 break; 167 } 168 169 #ifdef CONFIG_TARGET_LS1088AQDS 170 printf("FPGA: v%d (%s), build %d", 171 (int)QIXIS_READ(scver), qixis_read_tag(buf), 172 (int)qixis_read_minor()); 173 /* the timestamp string contains "\n" at the end */ 174 printf(" on %s", qixis_read_time(buf)); 175 #else 176 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); 177 #endif 178 179 /* 180 * Display the actual SERDES reference clocks as configured by the 181 * dip switches on the board. Note that the SWx registers could 182 * technically be set to force the reference clocks to match the 183 * values that the SERDES expects (or vice versa). For now, however, 184 * we just display both values and hope the user notices when they 185 * don't match. 186 */ 187 puts("SERDES1 Reference : "); 188 sw = QIXIS_READ(brdcfg[2]); 189 clock = (sw >> 6) & 3; 190 printf("Clock1 = %sMHz ", freq[clock]); 191 clock = (sw >> 4) & 3; 192 printf("Clock2 = %sMHz", freq[clock]); 193 194 puts("\nSERDES2 Reference : "); 195 clock = (sw >> 2) & 3; 196 printf("Clock1 = %sMHz ", freq[clock]); 197 clock = (sw >> 0) & 3; 198 printf("Clock2 = %sMHz\n", freq[clock]); 199 200 return 0; 201 } 202 #endif 203 204 bool if_board_diff_clk(void) 205 { 206 #ifdef CONFIG_TARGET_LS1088AQDS 207 u8 diff_conf = QIXIS_READ(brdcfg[11]); 208 return diff_conf & 0x40; 209 #else 210 u8 diff_conf = QIXIS_READ(dutcfg[11]); 211 return diff_conf & 0x80; 212 #endif 213 } 214 215 unsigned long get_board_sys_clk(void) 216 { 217 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 218 219 switch (sysclk_conf & 0x0f) { 220 case QIXIS_SYSCLK_83: 221 return 83333333; 222 case QIXIS_SYSCLK_100: 223 return 100000000; 224 case QIXIS_SYSCLK_125: 225 return 125000000; 226 case QIXIS_SYSCLK_133: 227 return 133333333; 228 case QIXIS_SYSCLK_150: 229 return 150000000; 230 case QIXIS_SYSCLK_160: 231 return 160000000; 232 case QIXIS_SYSCLK_166: 233 return 166666666; 234 } 235 236 return 66666666; 237 } 238 239 unsigned long get_board_ddr_clk(void) 240 { 241 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 242 243 if (if_board_diff_clk()) 244 return get_board_sys_clk(); 245 switch ((ddrclk_conf & 0x30) >> 4) { 246 case QIXIS_DDRCLK_100: 247 return 100000000; 248 case QIXIS_DDRCLK_125: 249 return 125000000; 250 case QIXIS_DDRCLK_133: 251 return 133333333; 252 } 253 254 return 66666666; 255 } 256 257 int select_i2c_ch_pca9547(u8 ch) 258 { 259 int ret; 260 261 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 262 if (ret) { 263 puts("PCA: failed to select proper channel\n"); 264 return ret; 265 } 266 267 return 0; 268 } 269 270 #if !defined(CONFIG_SPL_BUILD) 271 void board_retimer_init(void) 272 { 273 u8 reg; 274 275 /* Retimer is connected to I2C1_CH5 */ 276 select_i2c_ch_pca9547(I2C_MUX_CH5); 277 278 /* Access to Control/Shared register */ 279 reg = 0x0; 280 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 281 282 /* Read device revision and ID */ 283 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); 284 debug("Retimer version id = 0x%x\n", reg); 285 286 /* Enable Broadcast. All writes target all channel register sets */ 287 reg = 0x0c; 288 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 289 290 /* Reset Channel Registers */ 291 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); 292 reg |= 0x4; 293 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); 294 295 /* Set data rate as 10.3125 Gbps */ 296 reg = 0x90; 297 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); 298 reg = 0xb3; 299 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); 300 reg = 0x90; 301 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); 302 reg = 0xb3; 303 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); 304 reg = 0xcd; 305 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); 306 307 /* Select VCO Divider to full rate (000) */ 308 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); 309 reg &= 0x0f; 310 reg |= 0x70; 311 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); 312 313 #ifdef CONFIG_TARGET_LS1088AQDS 314 /* Retimer is connected to I2C1_CH5 */ 315 select_i2c_ch_pca9547(I2C_MUX_CH5); 316 317 /* Access to Control/Shared register */ 318 reg = 0x0; 319 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); 320 321 /* Read device revision and ID */ 322 i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1); 323 debug("Retimer version id = 0x%x\n", reg); 324 325 /* Enable Broadcast. All writes target all channel register sets */ 326 reg = 0x0c; 327 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); 328 329 /* Reset Channel Registers */ 330 i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1); 331 reg |= 0x4; 332 i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1); 333 334 /* Set data rate as 10.3125 Gbps */ 335 reg = 0x90; 336 i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1); 337 reg = 0xb3; 338 i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1); 339 reg = 0x90; 340 i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1); 341 reg = 0xb3; 342 i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1); 343 reg = 0xcd; 344 i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1); 345 346 /* Select VCO Divider to full rate (000) */ 347 i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); 348 reg &= 0x0f; 349 reg |= 0x70; 350 i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); 351 #endif 352 /*return the default channel*/ 353 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 354 } 355 356 #ifdef CONFIG_MISC_INIT_R 357 int misc_init_r(void) 358 { 359 #ifdef CONFIG_TARGET_LS1088ARDB 360 u8 brdcfg5; 361 362 if (hwconfig("esdhc-force-sd")) { 363 brdcfg5 = QIXIS_READ(brdcfg[5]); 364 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK; 365 brdcfg5 |= BRDCFG5_FORCE_SD; 366 QIXIS_WRITE(brdcfg[5], brdcfg5); 367 } 368 #endif 369 return 0; 370 } 371 #endif 372 #endif 373 374 int i2c_multiplexer_select_vid_channel(u8 channel) 375 { 376 return select_i2c_ch_pca9547(channel); 377 } 378 379 #ifdef CONFIG_TARGET_LS1088AQDS 380 /* read the current value(SVDD) of the LTM Regulator Voltage */ 381 int get_serdes_volt(void) 382 { 383 int ret, vcode = 0; 384 u8 chan = PWM_CHANNEL0; 385 386 /* Select the PAGE 0 using PMBus commands PAGE for VDD */ 387 ret = i2c_write(I2C_SVDD_MONITOR_ADDR, 388 PMBUS_CMD_PAGE, 1, &chan, 1); 389 if (ret) { 390 printf("VID: failed to select VDD Page 0\n"); 391 return ret; 392 } 393 394 /* Read the output voltage using PMBus command READ_VOUT */ 395 ret = i2c_read(I2C_SVDD_MONITOR_ADDR, 396 PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); 397 if (ret) { 398 printf("VID: failed to read the volatge\n"); 399 return ret; 400 } 401 402 return vcode; 403 } 404 405 int set_serdes_volt(int svdd) 406 { 407 int ret, vdd_last; 408 u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, 409 svdd & 0xFF, (svdd & 0xFF00) >> 8}; 410 411 /* Write the desired voltage code to the SVDD regulator */ 412 ret = i2c_write(I2C_SVDD_MONITOR_ADDR, 413 PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); 414 if (ret) { 415 printf("VID: I2C failed to write to the volatge regulator\n"); 416 return -1; 417 } 418 419 /* Wait for the volatge to get to the desired value */ 420 do { 421 vdd_last = get_serdes_volt(); 422 if (vdd_last < 0) { 423 printf("VID: Couldn't read sensor abort VID adjust\n"); 424 return -1; 425 } 426 } while (vdd_last != svdd); 427 428 return 1; 429 } 430 #else 431 int get_serdes_volt(void) 432 { 433 return 0; 434 } 435 436 int set_serdes_volt(int svdd) 437 { 438 int ret; 439 u8 brdcfg4; 440 441 printf("SVDD changing of RDB\n"); 442 443 /* Read the BRDCFG54 via CLPD */ 444 ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR, 445 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); 446 if (ret) { 447 printf("VID: I2C failed to read the CPLD BRDCFG4\n"); 448 return -1; 449 } 450 451 brdcfg4 = brdcfg4 | 0x08; 452 453 /* Write to the BRDCFG4 */ 454 ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 455 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); 456 if (ret) { 457 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n"); 458 return -1; 459 } 460 461 /* Wait for the volatge to get to the desired value */ 462 udelay(10000); 463 464 return 1; 465 } 466 #endif 467 468 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/ 469 int board_adjust_vdd(int vdd) 470 { 471 int ret = 0; 472 473 debug("%s: vdd = %d\n", __func__, vdd); 474 475 /* Special settings to be performed when voltage is 900mV */ 476 if (vdd == 900) { 477 ret = setup_serdes_volt(vdd); 478 if (ret < 0) { 479 ret = -1; 480 goto exit; 481 } 482 } 483 exit: 484 return ret; 485 } 486 487 #if !defined(CONFIG_SPL_BUILD) 488 int board_init(void) 489 { 490 init_final_memctl_regs(); 491 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) 492 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; 493 #endif 494 495 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 496 board_retimer_init(); 497 498 #ifdef CONFIG_ENV_IS_NOWHERE 499 gd->env_addr = (ulong)&default_environment[0]; 500 #endif 501 502 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) 503 /* invert AQR105 IRQ pins polarity */ 504 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK); 505 #endif 506 507 #ifdef CONFIG_FSL_CAAM 508 sec_init(); 509 #endif 510 #ifdef CONFIG_FSL_LS_PPA 511 ppa_init(); 512 #endif 513 return 0; 514 } 515 516 void detail_board_ddr_info(void) 517 { 518 puts("\nDDR "); 519 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); 520 print_ddr_info(0); 521 } 522 523 #if defined(CONFIG_ARCH_MISC_INIT) 524 int arch_misc_init(void) 525 { 526 return 0; 527 } 528 #endif 529 530 #ifdef CONFIG_FSL_MC_ENET 531 void fdt_fixup_board_enet(void *fdt) 532 { 533 int offset; 534 535 offset = fdt_path_offset(fdt, "/fsl-mc"); 536 537 if (offset < 0) 538 offset = fdt_path_offset(fdt, "/fsl,dprc@0"); 539 540 if (offset < 0) { 541 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", 542 __func__, offset); 543 return; 544 } 545 546 if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) 547 fdt_status_okay(fdt, offset); 548 else 549 fdt_status_fail(fdt, offset); 550 } 551 #endif 552 553 #ifdef CONFIG_OF_BOARD_SETUP 554 void fsl_fdt_fixup_flash(void *fdt) 555 { 556 int offset; 557 #ifdef CONFIG_TFABOOT 558 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; 559 u32 val; 560 #endif 561 562 /* 563 * IFC-NOR and QSPI are muxed on SoC. 564 * So disable IFC node in dts if QSPI is enabled or 565 * disable QSPI node in dts in case QSPI is not enabled. 566 */ 567 568 #ifdef CONFIG_TFABOOT 569 enum boot_src src = get_boot_src(); 570 bool disable_ifc = false; 571 572 switch (src) { 573 case BOOT_SOURCE_IFC_NOR: 574 disable_ifc = false; 575 break; 576 case BOOT_SOURCE_QSPI_NOR: 577 disable_ifc = true; 578 break; 579 default: 580 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4); 581 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3)) 582 disable_ifc = true; 583 break; 584 } 585 586 if (disable_ifc) { 587 offset = fdt_path_offset(fdt, "/soc/ifc/nor"); 588 589 if (offset < 0) 590 offset = fdt_path_offset(fdt, "/ifc/nor"); 591 } else { 592 offset = fdt_path_offset(fdt, "/soc/quadspi"); 593 594 if (offset < 0) 595 offset = fdt_path_offset(fdt, "/quadspi"); 596 } 597 598 #else 599 #ifdef CONFIG_FSL_QSPI 600 offset = fdt_path_offset(fdt, "/soc/ifc/nor"); 601 602 if (offset < 0) 603 offset = fdt_path_offset(fdt, "/ifc/nor"); 604 #else 605 offset = fdt_path_offset(fdt, "/soc/quadspi"); 606 607 if (offset < 0) 608 offset = fdt_path_offset(fdt, "/quadspi"); 609 #endif 610 #endif 611 if (offset < 0) 612 return; 613 614 fdt_status_disabled(fdt, offset); 615 } 616 617 int ft_board_setup(void *blob, bd_t *bd) 618 { 619 int err, i; 620 u64 base[CONFIG_NR_DRAM_BANKS]; 621 u64 size[CONFIG_NR_DRAM_BANKS]; 622 623 ft_cpu_setup(blob, bd); 624 625 /* fixup DT for the two GPP DDR banks */ 626 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 627 base[i] = gd->bd->bi_dram[i].start; 628 size[i] = gd->bd->bi_dram[i].size; 629 } 630 631 #ifdef CONFIG_RESV_RAM 632 /* reduce size if reserved memory is within this bank */ 633 if (gd->arch.resv_ram >= base[0] && 634 gd->arch.resv_ram < base[0] + size[0]) 635 size[0] = gd->arch.resv_ram - base[0]; 636 else if (gd->arch.resv_ram >= base[1] && 637 gd->arch.resv_ram < base[1] + size[1]) 638 size[1] = gd->arch.resv_ram - base[1]; 639 #endif 640 641 fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); 642 643 fdt_fsl_mc_fixup_iommu_map_entry(blob); 644 645 fsl_fdt_fixup_flash(blob); 646 647 #ifdef CONFIG_FSL_MC_ENET 648 fdt_fixup_board_enet(blob); 649 err = fsl_mc_ldpaa_exit(bd); 650 if (err) 651 return err; 652 #endif 653 if (is_pb_board()) 654 fixup_ls1088ardb_pb_banner(blob); 655 656 return 0; 657 } 658 #endif 659 #endif /* defined(CONFIG_SPL_BUILD) */ 660 661 #ifdef CONFIG_TFABOOT 662 #ifdef CONFIG_MTD_NOR_FLASH 663 int is_flash_available(void) 664 { 665 char *env_hwconfig = env_get("hwconfig"); 666 enum boot_src src = get_boot_src(); 667 int is_nor_flash_available = 1; 668 669 switch (src) { 670 case BOOT_SOURCE_IFC_NOR: 671 is_nor_flash_available = 1; 672 break; 673 case BOOT_SOURCE_QSPI_NOR: 674 is_nor_flash_available = 0; 675 break; 676 /* 677 * In Case of SD boot,if qspi is defined in env_hwconfig 678 * disable nor flash probe. 679 */ 680 default: 681 if (hwconfig_f("qspi", env_hwconfig)) 682 is_nor_flash_available = 0; 683 break; 684 } 685 return is_nor_flash_available; 686 } 687 #endif 688 689 void *env_sf_get_env_addr(void) 690 { 691 return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); 692 } 693 #endif 694