183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2e84a324bSAshish Kumar /*
35b595df3SPramod Kumar * Copyright 2017-2018 NXP
4e84a324bSAshish Kumar */
5e84a324bSAshish Kumar #include <common.h>
6e84a324bSAshish Kumar #include <i2c.h>
7e84a324bSAshish Kumar #include <malloc.h>
8e84a324bSAshish Kumar #include <errno.h>
9e84a324bSAshish Kumar #include <netdev.h>
10e84a324bSAshish Kumar #include <fsl_ifc.h>
11e84a324bSAshish Kumar #include <fsl_ddr.h>
12e84a324bSAshish Kumar #include <fsl_sec.h>
13e84a324bSAshish Kumar #include <asm/io.h>
14e84a324bSAshish Kumar #include <fdt_support.h>
15b08c8c48SMasahiro Yamada #include <linux/libfdt.h>
16e84a324bSAshish Kumar #include <fsl-mc/fsl_mc.h>
17e84a324bSAshish Kumar #include <environment.h>
18e84a324bSAshish Kumar #include <asm/arch-fsl-layerscape/soc.h>
19e84a324bSAshish Kumar #include <asm/arch/ppa.h>
2044cdb5b6SYangbo Lu #include <hwconfig.h>
21ef0789b7SRajesh Bhagat #include <asm/arch/fsl_serdes.h>
22ef0789b7SRajesh Bhagat #include <asm/arch/soc.h>
23e84a324bSAshish Kumar
24e84a324bSAshish Kumar #include "../common/qixis.h"
25e84a324bSAshish Kumar #include "ls1088a_qixis.h"
26ef0789b7SRajesh Bhagat #include "../common/vid.h"
27ef0789b7SRajesh Bhagat #include <fsl_immap.h>
28e84a324bSAshish Kumar
29e84a324bSAshish Kumar DECLARE_GLOBAL_DATA_PTR;
30e84a324bSAshish Kumar
311a12b4a0SPankit Garg #ifdef CONFIG_TARGET_LS1088AQDS
321a12b4a0SPankit Garg #ifdef CONFIG_TFABOOT
331a12b4a0SPankit Garg struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
341a12b4a0SPankit Garg {
351a12b4a0SPankit Garg "nor0",
361a12b4a0SPankit Garg CONFIG_SYS_NOR0_CSPR_EARLY,
371a12b4a0SPankit Garg CONFIG_SYS_NOR0_CSPR_EXT,
381a12b4a0SPankit Garg CONFIG_SYS_NOR_AMASK,
391a12b4a0SPankit Garg CONFIG_SYS_NOR_CSOR,
401a12b4a0SPankit Garg {
411a12b4a0SPankit Garg CONFIG_SYS_NOR_FTIM0,
421a12b4a0SPankit Garg CONFIG_SYS_NOR_FTIM1,
431a12b4a0SPankit Garg CONFIG_SYS_NOR_FTIM2,
441a12b4a0SPankit Garg CONFIG_SYS_NOR_FTIM3
451a12b4a0SPankit Garg },
461a12b4a0SPankit Garg 0,
471a12b4a0SPankit Garg CONFIG_SYS_NOR0_CSPR,
481a12b4a0SPankit Garg 0,
491a12b4a0SPankit Garg },
501a12b4a0SPankit Garg {
511a12b4a0SPankit Garg "nor1",
521a12b4a0SPankit Garg CONFIG_SYS_NOR1_CSPR_EARLY,
531a12b4a0SPankit Garg CONFIG_SYS_NOR0_CSPR_EXT,
541a12b4a0SPankit Garg CONFIG_SYS_NOR_AMASK_EARLY,
551a12b4a0SPankit Garg CONFIG_SYS_NOR_CSOR,
561a12b4a0SPankit Garg {
571a12b4a0SPankit Garg CONFIG_SYS_NOR_FTIM0,
581a12b4a0SPankit Garg CONFIG_SYS_NOR_FTIM1,
591a12b4a0SPankit Garg CONFIG_SYS_NOR_FTIM2,
601a12b4a0SPankit Garg CONFIG_SYS_NOR_FTIM3
611a12b4a0SPankit Garg },
621a12b4a0SPankit Garg 0,
631a12b4a0SPankit Garg CONFIG_SYS_NOR1_CSPR,
641a12b4a0SPankit Garg CONFIG_SYS_NOR_AMASK,
651a12b4a0SPankit Garg },
661a12b4a0SPankit Garg {
671a12b4a0SPankit Garg "nand",
681a12b4a0SPankit Garg CONFIG_SYS_NAND_CSPR,
691a12b4a0SPankit Garg CONFIG_SYS_NAND_CSPR_EXT,
701a12b4a0SPankit Garg CONFIG_SYS_NAND_AMASK,
711a12b4a0SPankit Garg CONFIG_SYS_NAND_CSOR,
721a12b4a0SPankit Garg {
731a12b4a0SPankit Garg CONFIG_SYS_NAND_FTIM0,
741a12b4a0SPankit Garg CONFIG_SYS_NAND_FTIM1,
751a12b4a0SPankit Garg CONFIG_SYS_NAND_FTIM2,
761a12b4a0SPankit Garg CONFIG_SYS_NAND_FTIM3
771a12b4a0SPankit Garg },
781a12b4a0SPankit Garg },
791a12b4a0SPankit Garg {
801a12b4a0SPankit Garg "fpga",
811a12b4a0SPankit Garg CONFIG_SYS_FPGA_CSPR,
821a12b4a0SPankit Garg CONFIG_SYS_FPGA_CSPR_EXT,
831a12b4a0SPankit Garg SYS_FPGA_AMASK,
841a12b4a0SPankit Garg CONFIG_SYS_FPGA_CSOR,
851a12b4a0SPankit Garg {
861a12b4a0SPankit Garg SYS_FPGA_CS_FTIM0,
871a12b4a0SPankit Garg SYS_FPGA_CS_FTIM1,
881a12b4a0SPankit Garg SYS_FPGA_CS_FTIM2,
891a12b4a0SPankit Garg SYS_FPGA_CS_FTIM3
901a12b4a0SPankit Garg },
911a12b4a0SPankit Garg 0,
921a12b4a0SPankit Garg SYS_FPGA_CSPR_FINAL,
931a12b4a0SPankit Garg 0,
941a12b4a0SPankit Garg }
951a12b4a0SPankit Garg };
961a12b4a0SPankit Garg
971a12b4a0SPankit Garg struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
981a12b4a0SPankit Garg {
991a12b4a0SPankit Garg "nand",
1001a12b4a0SPankit Garg CONFIG_SYS_NAND_CSPR,
1011a12b4a0SPankit Garg CONFIG_SYS_NAND_CSPR_EXT,
1021a12b4a0SPankit Garg CONFIG_SYS_NAND_AMASK,
1031a12b4a0SPankit Garg CONFIG_SYS_NAND_CSOR,
1041a12b4a0SPankit Garg {
1051a12b4a0SPankit Garg CONFIG_SYS_NAND_FTIM0,
1061a12b4a0SPankit Garg CONFIG_SYS_NAND_FTIM1,
1071a12b4a0SPankit Garg CONFIG_SYS_NAND_FTIM2,
1081a12b4a0SPankit Garg CONFIG_SYS_NAND_FTIM3
1091a12b4a0SPankit Garg },
1101a12b4a0SPankit Garg },
1111a12b4a0SPankit Garg {
1121a12b4a0SPankit Garg "reserved",
1131a12b4a0SPankit Garg },
1141a12b4a0SPankit Garg {
1151a12b4a0SPankit Garg "fpga",
1161a12b4a0SPankit Garg CONFIG_SYS_FPGA_CSPR,
1171a12b4a0SPankit Garg CONFIG_SYS_FPGA_CSPR_EXT,
1181a12b4a0SPankit Garg SYS_FPGA_AMASK,
1191a12b4a0SPankit Garg CONFIG_SYS_FPGA_CSOR,
1201a12b4a0SPankit Garg {
1211a12b4a0SPankit Garg SYS_FPGA_CS_FTIM0,
1221a12b4a0SPankit Garg SYS_FPGA_CS_FTIM1,
1231a12b4a0SPankit Garg SYS_FPGA_CS_FTIM2,
1241a12b4a0SPankit Garg SYS_FPGA_CS_FTIM3
1251a12b4a0SPankit Garg },
1261a12b4a0SPankit Garg 0,
1271a12b4a0SPankit Garg SYS_FPGA_CSPR_FINAL,
1281a12b4a0SPankit Garg 0,
1291a12b4a0SPankit Garg }
1301a12b4a0SPankit Garg };
1311a12b4a0SPankit Garg
ifc_cfg_boot_info(struct ifc_regs_info * regs_info)1321a12b4a0SPankit Garg void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
1331a12b4a0SPankit Garg {
1341a12b4a0SPankit Garg enum boot_src src = get_boot_src();
1351a12b4a0SPankit Garg
1361a12b4a0SPankit Garg if (src == BOOT_SOURCE_QSPI_NOR)
1371a12b4a0SPankit Garg regs_info->regs = ifc_cfg_qspi_nor_boot;
1381a12b4a0SPankit Garg else
1391a12b4a0SPankit Garg regs_info->regs = ifc_cfg_ifc_nor_boot;
1401a12b4a0SPankit Garg
1411a12b4a0SPankit Garg regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
1421a12b4a0SPankit Garg }
1431a12b4a0SPankit Garg #endif /* CONFIG_TFABOOT */
1441a12b4a0SPankit Garg #endif /* CONFIG_TARGET_LS1088AQDS */
1451a12b4a0SPankit Garg
board_early_init_f(void)14610e7eaf0SSumit Garg int board_early_init_f(void)
14710e7eaf0SSumit Garg {
148169d493bSAshish Kumar #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
149169d493bSAshish Kumar i2c_early_init_f();
150169d493bSAshish Kumar #endif
15110e7eaf0SSumit Garg fsl_lsch3_early_init_f();
15210e7eaf0SSumit Garg return 0;
15310e7eaf0SSumit Garg }
15410e7eaf0SSumit Garg
15510e7eaf0SSumit Garg #ifdef CONFIG_FSL_QIXIS
get_qixis_addr(void)156e84a324bSAshish Kumar unsigned long long get_qixis_addr(void)
157e84a324bSAshish Kumar {
158e84a324bSAshish Kumar unsigned long long addr;
159e84a324bSAshish Kumar
160e84a324bSAshish Kumar if (gd->flags & GD_FLG_RELOC)
161e84a324bSAshish Kumar addr = QIXIS_BASE_PHYS;
162e84a324bSAshish Kumar else
163e84a324bSAshish Kumar addr = QIXIS_BASE_PHYS_EARLY;
164e84a324bSAshish Kumar
165e84a324bSAshish Kumar /*
166e84a324bSAshish Kumar * IFC address under 256MB is mapped to 0x30000000, any address above
167e84a324bSAshish Kumar * is mapped to 0x5_10000000 up to 4GB.
168e84a324bSAshish Kumar */
169e84a324bSAshish Kumar addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
170e84a324bSAshish Kumar
171e84a324bSAshish Kumar return addr;
172e84a324bSAshish Kumar }
17310e7eaf0SSumit Garg #endif
174e84a324bSAshish Kumar
175ef0789b7SRajesh Bhagat #if defined(CONFIG_VID)
init_func_vid(void)176ef0789b7SRajesh Bhagat int init_func_vid(void)
177ef0789b7SRajesh Bhagat {
178ef0789b7SRajesh Bhagat if (adjust_vdd(0) < 0)
179ef0789b7SRajesh Bhagat printf("core voltage not adjusted\n");
180ef0789b7SRajesh Bhagat
181ef0789b7SRajesh Bhagat return 0;
182ef0789b7SRajesh Bhagat }
183ef0789b7SRajesh Bhagat #endif
184ef0789b7SRajesh Bhagat
is_pb_board(void)1855b595df3SPramod Kumar int is_pb_board(void)
1865b595df3SPramod Kumar {
1875b595df3SPramod Kumar u8 board_id;
1885b595df3SPramod Kumar
1895b595df3SPramod Kumar board_id = QIXIS_READ(id);
1905b595df3SPramod Kumar if (board_id == LS1088ARDB_PB_BOARD)
1915b595df3SPramod Kumar return 1;
1925b595df3SPramod Kumar else
1935b595df3SPramod Kumar return 0;
1945b595df3SPramod Kumar }
1955b595df3SPramod Kumar
fixup_ls1088ardb_pb_banner(void * fdt)1965b595df3SPramod Kumar int fixup_ls1088ardb_pb_banner(void *fdt)
1975b595df3SPramod Kumar {
1985b595df3SPramod Kumar fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
1995b595df3SPramod Kumar
2005b595df3SPramod Kumar return 0;
2015b595df3SPramod Kumar }
2025b595df3SPramod Kumar
20310e7eaf0SSumit Garg #if !defined(CONFIG_SPL_BUILD)
checkboard(void)204e84a324bSAshish Kumar int checkboard(void)
205e84a324bSAshish Kumar {
206143af3c6SPankit Garg #ifdef CONFIG_TFABOOT
207143af3c6SPankit Garg enum boot_src src = get_boot_src();
208143af3c6SPankit Garg #endif
209e84a324bSAshish Kumar char buf[64];
210e84a324bSAshish Kumar u8 sw;
211e84a324bSAshish Kumar static const char *const freq[] = {"100", "125", "156.25",
212e84a324bSAshish Kumar "100 separate SSCG"};
213e84a324bSAshish Kumar int clock;
214e84a324bSAshish Kumar
2157769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS
2167769776aSAshish Kumar printf("Board: LS1088A-QDS, ");
2177769776aSAshish Kumar #else
2185b595df3SPramod Kumar if (is_pb_board())
2195b595df3SPramod Kumar printf("Board: LS1088ARDB-PB, ");
2205b595df3SPramod Kumar else
221e84a324bSAshish Kumar printf("Board: LS1088A-RDB, ");
2227769776aSAshish Kumar #endif
223e84a324bSAshish Kumar
224e84a324bSAshish Kumar sw = QIXIS_READ(arch);
225e84a324bSAshish Kumar printf("Board Arch: V%d, ", sw >> 4);
226e84a324bSAshish Kumar
2277769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS
2287769776aSAshish Kumar printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
2297769776aSAshish Kumar #else
230e84a324bSAshish Kumar printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
2317769776aSAshish Kumar #endif
232e84a324bSAshish Kumar
233e84a324bSAshish Kumar memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
234e84a324bSAshish Kumar
235e84a324bSAshish Kumar sw = QIXIS_READ(brdcfg[0]);
236e84a324bSAshish Kumar sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
237e84a324bSAshish Kumar
238143af3c6SPankit Garg #ifdef CONFIG_TFABOOT
239143af3c6SPankit Garg if (src == BOOT_SOURCE_SD_MMC)
240143af3c6SPankit Garg puts("SD card\n");
241143af3c6SPankit Garg #else
242e84a324bSAshish Kumar #ifdef CONFIG_SD_BOOT
243e84a324bSAshish Kumar puts("SD card\n");
244e84a324bSAshish Kumar #endif
245143af3c6SPankit Garg #endif /* CONFIG_TFABOOT */
246e84a324bSAshish Kumar switch (sw) {
2477769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS
248e84a324bSAshish Kumar case 0:
2497769776aSAshish Kumar case 1:
2507769776aSAshish Kumar case 2:
2517769776aSAshish Kumar case 3:
2527769776aSAshish Kumar case 4:
2537769776aSAshish Kumar case 5:
2547769776aSAshish Kumar case 6:
2557769776aSAshish Kumar case 7:
2567769776aSAshish Kumar printf("vBank: %d\n", sw);
2577769776aSAshish Kumar break;
2587769776aSAshish Kumar case 8:
2597769776aSAshish Kumar puts("PromJet\n");
2607769776aSAshish Kumar break;
2617769776aSAshish Kumar case 15:
2627769776aSAshish Kumar puts("IFCCard\n");
2637769776aSAshish Kumar break;
2647769776aSAshish Kumar case 14:
2657769776aSAshish Kumar #else
2667769776aSAshish Kumar case 0:
2677769776aSAshish Kumar #endif
268e84a324bSAshish Kumar puts("QSPI:");
269e84a324bSAshish Kumar sw = QIXIS_READ(brdcfg[0]);
270e84a324bSAshish Kumar sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
271e84a324bSAshish Kumar if (sw == 0 || sw == 4)
272e84a324bSAshish Kumar puts("0\n");
273e84a324bSAshish Kumar else if (sw == 1)
274e84a324bSAshish Kumar puts("1\n");
275e84a324bSAshish Kumar else
276e84a324bSAshish Kumar puts("EMU\n");
277e84a324bSAshish Kumar break;
278e84a324bSAshish Kumar
279e84a324bSAshish Kumar default:
280e84a324bSAshish Kumar printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
281e84a324bSAshish Kumar break;
282e84a324bSAshish Kumar }
283e84a324bSAshish Kumar
2847769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS
2857769776aSAshish Kumar printf("FPGA: v%d (%s), build %d",
2867769776aSAshish Kumar (int)QIXIS_READ(scver), qixis_read_tag(buf),
2877769776aSAshish Kumar (int)qixis_read_minor());
2887769776aSAshish Kumar /* the timestamp string contains "\n" at the end */
2897769776aSAshish Kumar printf(" on %s", qixis_read_time(buf));
2907769776aSAshish Kumar #else
291e84a324bSAshish Kumar printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
2927769776aSAshish Kumar #endif
293e84a324bSAshish Kumar
294e84a324bSAshish Kumar /*
295e84a324bSAshish Kumar * Display the actual SERDES reference clocks as configured by the
296e84a324bSAshish Kumar * dip switches on the board. Note that the SWx registers could
297e84a324bSAshish Kumar * technically be set to force the reference clocks to match the
298e84a324bSAshish Kumar * values that the SERDES expects (or vice versa). For now, however,
299e84a324bSAshish Kumar * we just display both values and hope the user notices when they
300e84a324bSAshish Kumar * don't match.
301e84a324bSAshish Kumar */
302e84a324bSAshish Kumar puts("SERDES1 Reference : ");
303e84a324bSAshish Kumar sw = QIXIS_READ(brdcfg[2]);
304e84a324bSAshish Kumar clock = (sw >> 6) & 3;
305e84a324bSAshish Kumar printf("Clock1 = %sMHz ", freq[clock]);
306e84a324bSAshish Kumar clock = (sw >> 4) & 3;
307e84a324bSAshish Kumar printf("Clock2 = %sMHz", freq[clock]);
308e84a324bSAshish Kumar
309e84a324bSAshish Kumar puts("\nSERDES2 Reference : ");
310e84a324bSAshish Kumar clock = (sw >> 2) & 3;
311e84a324bSAshish Kumar printf("Clock1 = %sMHz ", freq[clock]);
312e84a324bSAshish Kumar clock = (sw >> 0) & 3;
313e84a324bSAshish Kumar printf("Clock2 = %sMHz\n", freq[clock]);
314e84a324bSAshish Kumar
315e84a324bSAshish Kumar return 0;
316e84a324bSAshish Kumar }
317d12b166aSAshish Kumar #endif
318e84a324bSAshish Kumar
if_board_diff_clk(void)319e84a324bSAshish Kumar bool if_board_diff_clk(void)
320e84a324bSAshish Kumar {
3217769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS
3227769776aSAshish Kumar u8 diff_conf = QIXIS_READ(brdcfg[11]);
3237769776aSAshish Kumar return diff_conf & 0x40;
3247769776aSAshish Kumar #else
325e84a324bSAshish Kumar u8 diff_conf = QIXIS_READ(dutcfg[11]);
326e84a324bSAshish Kumar return diff_conf & 0x80;
3277769776aSAshish Kumar #endif
328e84a324bSAshish Kumar }
329e84a324bSAshish Kumar
get_board_sys_clk(void)330e84a324bSAshish Kumar unsigned long get_board_sys_clk(void)
331e84a324bSAshish Kumar {
332e84a324bSAshish Kumar u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
333e84a324bSAshish Kumar
334e84a324bSAshish Kumar switch (sysclk_conf & 0x0f) {
335e84a324bSAshish Kumar case QIXIS_SYSCLK_83:
336e84a324bSAshish Kumar return 83333333;
337e84a324bSAshish Kumar case QIXIS_SYSCLK_100:
338e84a324bSAshish Kumar return 100000000;
339e84a324bSAshish Kumar case QIXIS_SYSCLK_125:
340e84a324bSAshish Kumar return 125000000;
341e84a324bSAshish Kumar case QIXIS_SYSCLK_133:
342e84a324bSAshish Kumar return 133333333;
343e84a324bSAshish Kumar case QIXIS_SYSCLK_150:
344e84a324bSAshish Kumar return 150000000;
345e84a324bSAshish Kumar case QIXIS_SYSCLK_160:
346e84a324bSAshish Kumar return 160000000;
347e84a324bSAshish Kumar case QIXIS_SYSCLK_166:
348e84a324bSAshish Kumar return 166666666;
349e84a324bSAshish Kumar }
350e84a324bSAshish Kumar
351e84a324bSAshish Kumar return 66666666;
352e84a324bSAshish Kumar }
353e84a324bSAshish Kumar
get_board_ddr_clk(void)354e84a324bSAshish Kumar unsigned long get_board_ddr_clk(void)
355e84a324bSAshish Kumar {
356e84a324bSAshish Kumar u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
357e84a324bSAshish Kumar
358e84a324bSAshish Kumar if (if_board_diff_clk())
359e84a324bSAshish Kumar return get_board_sys_clk();
360e84a324bSAshish Kumar switch ((ddrclk_conf & 0x30) >> 4) {
361e84a324bSAshish Kumar case QIXIS_DDRCLK_100:
362e84a324bSAshish Kumar return 100000000;
363e84a324bSAshish Kumar case QIXIS_DDRCLK_125:
364e84a324bSAshish Kumar return 125000000;
365e84a324bSAshish Kumar case QIXIS_DDRCLK_133:
366e84a324bSAshish Kumar return 133333333;
367e84a324bSAshish Kumar }
368e84a324bSAshish Kumar
369e84a324bSAshish Kumar return 66666666;
370e84a324bSAshish Kumar }
371e84a324bSAshish Kumar
select_i2c_ch_pca9547(u8 ch)372e84a324bSAshish Kumar int select_i2c_ch_pca9547(u8 ch)
373e84a324bSAshish Kumar {
374e84a324bSAshish Kumar int ret;
375e84a324bSAshish Kumar
376e84a324bSAshish Kumar ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
377e84a324bSAshish Kumar if (ret) {
378e84a324bSAshish Kumar puts("PCA: failed to select proper channel\n");
379e84a324bSAshish Kumar return ret;
380e84a324bSAshish Kumar }
381e84a324bSAshish Kumar
382e84a324bSAshish Kumar return 0;
383e84a324bSAshish Kumar }
384e84a324bSAshish Kumar
385980d61a2SRajesh Bhagat #if !defined(CONFIG_SPL_BUILD)
board_retimer_init(void)386e84a324bSAshish Kumar void board_retimer_init(void)
387e84a324bSAshish Kumar {
388e84a324bSAshish Kumar u8 reg;
389e84a324bSAshish Kumar
390e84a324bSAshish Kumar /* Retimer is connected to I2C1_CH5 */
391e84a324bSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH5);
392e84a324bSAshish Kumar
393e84a324bSAshish Kumar /* Access to Control/Shared register */
394e84a324bSAshish Kumar reg = 0x0;
395e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
396e84a324bSAshish Kumar
397e84a324bSAshish Kumar /* Read device revision and ID */
398e84a324bSAshish Kumar i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
399e84a324bSAshish Kumar debug("Retimer version id = 0x%x\n", reg);
400e84a324bSAshish Kumar
401e84a324bSAshish Kumar /* Enable Broadcast. All writes target all channel register sets */
402e84a324bSAshish Kumar reg = 0x0c;
403e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
404e84a324bSAshish Kumar
405e84a324bSAshish Kumar /* Reset Channel Registers */
406e84a324bSAshish Kumar i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
407e84a324bSAshish Kumar reg |= 0x4;
408e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
409e84a324bSAshish Kumar
410e84a324bSAshish Kumar /* Set data rate as 10.3125 Gbps */
411e84a324bSAshish Kumar reg = 0x90;
412e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
413e84a324bSAshish Kumar reg = 0xb3;
414e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
415e84a324bSAshish Kumar reg = 0x90;
416e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
417e84a324bSAshish Kumar reg = 0xb3;
418e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
419e84a324bSAshish Kumar reg = 0xcd;
420e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
421e84a324bSAshish Kumar
422e84a324bSAshish Kumar /* Select VCO Divider to full rate (000) */
423e84a324bSAshish Kumar i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
424e84a324bSAshish Kumar reg &= 0x0f;
425e84a324bSAshish Kumar reg |= 0x70;
426e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
427e84a324bSAshish Kumar
4287769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS
4297769776aSAshish Kumar /* Retimer is connected to I2C1_CH5 */
4307769776aSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH5);
431e84a324bSAshish Kumar
4327769776aSAshish Kumar /* Access to Control/Shared register */
4337769776aSAshish Kumar reg = 0x0;
4347769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
4357769776aSAshish Kumar
4367769776aSAshish Kumar /* Read device revision and ID */
4377769776aSAshish Kumar i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
4387769776aSAshish Kumar debug("Retimer version id = 0x%x\n", reg);
4397769776aSAshish Kumar
4407769776aSAshish Kumar /* Enable Broadcast. All writes target all channel register sets */
4417769776aSAshish Kumar reg = 0x0c;
4427769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
4437769776aSAshish Kumar
4447769776aSAshish Kumar /* Reset Channel Registers */
4457769776aSAshish Kumar i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
4467769776aSAshish Kumar reg |= 0x4;
4477769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
4487769776aSAshish Kumar
4497769776aSAshish Kumar /* Set data rate as 10.3125 Gbps */
4507769776aSAshish Kumar reg = 0x90;
4517769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
4527769776aSAshish Kumar reg = 0xb3;
4537769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
4547769776aSAshish Kumar reg = 0x90;
4557769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
4567769776aSAshish Kumar reg = 0xb3;
4577769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
4587769776aSAshish Kumar reg = 0xcd;
4597769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
4607769776aSAshish Kumar
4617769776aSAshish Kumar /* Select VCO Divider to full rate (000) */
4627769776aSAshish Kumar i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
4637769776aSAshish Kumar reg &= 0x0f;
4647769776aSAshish Kumar reg |= 0x70;
4657769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
4667769776aSAshish Kumar #endif
467e84a324bSAshish Kumar /*return the default channel*/
468e84a324bSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
469e84a324bSAshish Kumar }
470e84a324bSAshish Kumar
47144cdb5b6SYangbo Lu #ifdef CONFIG_MISC_INIT_R
misc_init_r(void)47244cdb5b6SYangbo Lu int misc_init_r(void)
47344cdb5b6SYangbo Lu {
47444cdb5b6SYangbo Lu #ifdef CONFIG_TARGET_LS1088ARDB
47544cdb5b6SYangbo Lu u8 brdcfg5;
47644cdb5b6SYangbo Lu
47744cdb5b6SYangbo Lu if (hwconfig("esdhc-force-sd")) {
47844cdb5b6SYangbo Lu brdcfg5 = QIXIS_READ(brdcfg[5]);
47944cdb5b6SYangbo Lu brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
48044cdb5b6SYangbo Lu brdcfg5 |= BRDCFG5_FORCE_SD;
48144cdb5b6SYangbo Lu QIXIS_WRITE(brdcfg[5], brdcfg5);
48244cdb5b6SYangbo Lu }
48344cdb5b6SYangbo Lu #endif
48444cdb5b6SYangbo Lu return 0;
48544cdb5b6SYangbo Lu }
48644cdb5b6SYangbo Lu #endif
487980d61a2SRajesh Bhagat #endif
48844cdb5b6SYangbo Lu
i2c_multiplexer_select_vid_channel(u8 channel)489ef0789b7SRajesh Bhagat int i2c_multiplexer_select_vid_channel(u8 channel)
490ef0789b7SRajesh Bhagat {
491ef0789b7SRajesh Bhagat return select_i2c_ch_pca9547(channel);
492ef0789b7SRajesh Bhagat }
493ef0789b7SRajesh Bhagat
494ef0789b7SRajesh Bhagat #ifdef CONFIG_TARGET_LS1088AQDS
495ef0789b7SRajesh Bhagat /* read the current value(SVDD) of the LTM Regulator Voltage */
get_serdes_volt(void)496ef0789b7SRajesh Bhagat int get_serdes_volt(void)
497ef0789b7SRajesh Bhagat {
498ef0789b7SRajesh Bhagat int ret, vcode = 0;
499ef0789b7SRajesh Bhagat u8 chan = PWM_CHANNEL0;
500ef0789b7SRajesh Bhagat
501ef0789b7SRajesh Bhagat /* Select the PAGE 0 using PMBus commands PAGE for VDD */
502ef0789b7SRajesh Bhagat ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
503ef0789b7SRajesh Bhagat PMBUS_CMD_PAGE, 1, &chan, 1);
504ef0789b7SRajesh Bhagat if (ret) {
505ef0789b7SRajesh Bhagat printf("VID: failed to select VDD Page 0\n");
506ef0789b7SRajesh Bhagat return ret;
507ef0789b7SRajesh Bhagat }
508ef0789b7SRajesh Bhagat
509ef0789b7SRajesh Bhagat /* Read the output voltage using PMBus command READ_VOUT */
510ef0789b7SRajesh Bhagat ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
511ef0789b7SRajesh Bhagat PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
512ef0789b7SRajesh Bhagat if (ret) {
513ef0789b7SRajesh Bhagat printf("VID: failed to read the volatge\n");
514ef0789b7SRajesh Bhagat return ret;
515ef0789b7SRajesh Bhagat }
516ef0789b7SRajesh Bhagat
517ef0789b7SRajesh Bhagat return vcode;
518ef0789b7SRajesh Bhagat }
519ef0789b7SRajesh Bhagat
set_serdes_volt(int svdd)520ef0789b7SRajesh Bhagat int set_serdes_volt(int svdd)
521ef0789b7SRajesh Bhagat {
522ef0789b7SRajesh Bhagat int ret, vdd_last;
523ef0789b7SRajesh Bhagat u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
524ef0789b7SRajesh Bhagat svdd & 0xFF, (svdd & 0xFF00) >> 8};
525ef0789b7SRajesh Bhagat
526ef0789b7SRajesh Bhagat /* Write the desired voltage code to the SVDD regulator */
527ef0789b7SRajesh Bhagat ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
528ef0789b7SRajesh Bhagat PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
529ef0789b7SRajesh Bhagat if (ret) {
530ef0789b7SRajesh Bhagat printf("VID: I2C failed to write to the volatge regulator\n");
531ef0789b7SRajesh Bhagat return -1;
532ef0789b7SRajesh Bhagat }
533ef0789b7SRajesh Bhagat
534ef0789b7SRajesh Bhagat /* Wait for the volatge to get to the desired value */
535ef0789b7SRajesh Bhagat do {
536ef0789b7SRajesh Bhagat vdd_last = get_serdes_volt();
537ef0789b7SRajesh Bhagat if (vdd_last < 0) {
538ef0789b7SRajesh Bhagat printf("VID: Couldn't read sensor abort VID adjust\n");
539ef0789b7SRajesh Bhagat return -1;
540ef0789b7SRajesh Bhagat }
541ef0789b7SRajesh Bhagat } while (vdd_last != svdd);
542ef0789b7SRajesh Bhagat
543ef0789b7SRajesh Bhagat return 1;
544ef0789b7SRajesh Bhagat }
545ef0789b7SRajesh Bhagat #else
get_serdes_volt(void)546ef0789b7SRajesh Bhagat int get_serdes_volt(void)
547ef0789b7SRajesh Bhagat {
548ef0789b7SRajesh Bhagat return 0;
549ef0789b7SRajesh Bhagat }
550ef0789b7SRajesh Bhagat
set_serdes_volt(int svdd)551ef0789b7SRajesh Bhagat int set_serdes_volt(int svdd)
552ef0789b7SRajesh Bhagat {
553ef0789b7SRajesh Bhagat int ret;
554ef0789b7SRajesh Bhagat u8 brdcfg4;
555ef0789b7SRajesh Bhagat
556ef0789b7SRajesh Bhagat printf("SVDD changing of RDB\n");
557ef0789b7SRajesh Bhagat
558ef0789b7SRajesh Bhagat /* Read the BRDCFG54 via CLPD */
559ef0789b7SRajesh Bhagat ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
560ef0789b7SRajesh Bhagat QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
561ef0789b7SRajesh Bhagat if (ret) {
562ef0789b7SRajesh Bhagat printf("VID: I2C failed to read the CPLD BRDCFG4\n");
563ef0789b7SRajesh Bhagat return -1;
564ef0789b7SRajesh Bhagat }
565ef0789b7SRajesh Bhagat
566ef0789b7SRajesh Bhagat brdcfg4 = brdcfg4 | 0x08;
567ef0789b7SRajesh Bhagat
568ef0789b7SRajesh Bhagat /* Write to the BRDCFG4 */
569ef0789b7SRajesh Bhagat ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
570ef0789b7SRajesh Bhagat QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
571ef0789b7SRajesh Bhagat if (ret) {
572ef0789b7SRajesh Bhagat debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
573ef0789b7SRajesh Bhagat return -1;
574ef0789b7SRajesh Bhagat }
575ef0789b7SRajesh Bhagat
576ef0789b7SRajesh Bhagat /* Wait for the volatge to get to the desired value */
577ef0789b7SRajesh Bhagat udelay(10000);
578ef0789b7SRajesh Bhagat
579ef0789b7SRajesh Bhagat return 1;
580ef0789b7SRajesh Bhagat }
581ef0789b7SRajesh Bhagat #endif
582ef0789b7SRajesh Bhagat
583ef0789b7SRajesh Bhagat /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
board_adjust_vdd(int vdd)584ef0789b7SRajesh Bhagat int board_adjust_vdd(int vdd)
585ef0789b7SRajesh Bhagat {
586ef0789b7SRajesh Bhagat int ret = 0;
587ef0789b7SRajesh Bhagat
588ef0789b7SRajesh Bhagat debug("%s: vdd = %d\n", __func__, vdd);
589ef0789b7SRajesh Bhagat
590ef0789b7SRajesh Bhagat /* Special settings to be performed when voltage is 900mV */
591ef0789b7SRajesh Bhagat if (vdd == 900) {
592ef0789b7SRajesh Bhagat ret = setup_serdes_volt(vdd);
593ef0789b7SRajesh Bhagat if (ret < 0) {
594ef0789b7SRajesh Bhagat ret = -1;
595ef0789b7SRajesh Bhagat goto exit;
596ef0789b7SRajesh Bhagat }
597ef0789b7SRajesh Bhagat }
598ef0789b7SRajesh Bhagat exit:
599ef0789b7SRajesh Bhagat return ret;
600ef0789b7SRajesh Bhagat }
601ef0789b7SRajesh Bhagat
602980d61a2SRajesh Bhagat #if !defined(CONFIG_SPL_BUILD)
board_init(void)603e84a324bSAshish Kumar int board_init(void)
604e84a324bSAshish Kumar {
605e84a324bSAshish Kumar init_final_memctl_regs();
606e84a324bSAshish Kumar #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
607e84a324bSAshish Kumar u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
608e84a324bSAshish Kumar #endif
609e84a324bSAshish Kumar
610e84a324bSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
611e84a324bSAshish Kumar board_retimer_init();
612e84a324bSAshish Kumar
613e84a324bSAshish Kumar #ifdef CONFIG_ENV_IS_NOWHERE
614e84a324bSAshish Kumar gd->env_addr = (ulong)&default_environment[0];
615e84a324bSAshish Kumar #endif
616e84a324bSAshish Kumar
617e84a324bSAshish Kumar #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
618e84a324bSAshish Kumar /* invert AQR105 IRQ pins polarity */
619e84a324bSAshish Kumar out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
620e84a324bSAshish Kumar #endif
621e84a324bSAshish Kumar
62230c41d21SUdit Agarwal #ifdef CONFIG_FSL_CAAM
62330c41d21SUdit Agarwal sec_init();
62430c41d21SUdit Agarwal #endif
625e84a324bSAshish Kumar #ifdef CONFIG_FSL_LS_PPA
626e84a324bSAshish Kumar ppa_init();
627e84a324bSAshish Kumar #endif
628e84a324bSAshish Kumar return 0;
629e84a324bSAshish Kumar }
630e84a324bSAshish Kumar
detail_board_ddr_info(void)631e84a324bSAshish Kumar void detail_board_ddr_info(void)
632e84a324bSAshish Kumar {
633e84a324bSAshish Kumar puts("\nDDR ");
634e84a324bSAshish Kumar print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
635e84a324bSAshish Kumar print_ddr_info(0);
636e84a324bSAshish Kumar }
637e84a324bSAshish Kumar
638e84a324bSAshish Kumar #if defined(CONFIG_ARCH_MISC_INIT)
arch_misc_init(void)639e84a324bSAshish Kumar int arch_misc_init(void)
640e84a324bSAshish Kumar {
641e84a324bSAshish Kumar return 0;
642e84a324bSAshish Kumar }
643e84a324bSAshish Kumar #endif
644e84a324bSAshish Kumar
645e84a324bSAshish Kumar #ifdef CONFIG_FSL_MC_ENET
board_quiesce_devices(void)6464130780aSMian Yousaf Kaukab void board_quiesce_devices(void)
6474130780aSMian Yousaf Kaukab {
6484130780aSMian Yousaf Kaukab fsl_mc_ldpaa_exit(gd->bd);
6494130780aSMian Yousaf Kaukab }
6504130780aSMian Yousaf Kaukab
fdt_fixup_board_enet(void * fdt)651e84a324bSAshish Kumar void fdt_fixup_board_enet(void *fdt)
652e84a324bSAshish Kumar {
653e84a324bSAshish Kumar int offset;
654e84a324bSAshish Kumar
655e84a324bSAshish Kumar offset = fdt_path_offset(fdt, "/fsl-mc");
656e84a324bSAshish Kumar
657e84a324bSAshish Kumar if (offset < 0)
658*730bd565SMian Yousaf Kaukab offset = fdt_path_offset(fdt, "/soc/fsl-mc");
659e84a324bSAshish Kumar
660e84a324bSAshish Kumar if (offset < 0) {
661e84a324bSAshish Kumar printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
662e84a324bSAshish Kumar __func__, offset);
663e84a324bSAshish Kumar return;
664e84a324bSAshish Kumar }
665e84a324bSAshish Kumar
6667e968049SMian Yousaf Kaukab if (get_mc_boot_status() == 0 &&
6677e968049SMian Yousaf Kaukab (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
668e84a324bSAshish Kumar fdt_status_okay(fdt, offset);
669e84a324bSAshish Kumar else
670e84a324bSAshish Kumar fdt_status_fail(fdt, offset);
671e84a324bSAshish Kumar }
672e84a324bSAshish Kumar #endif
673e84a324bSAshish Kumar
674e84a324bSAshish Kumar #ifdef CONFIG_OF_BOARD_SETUP
fsl_fdt_fixup_flash(void * fdt)6756b6b7e8aSAshish Kumar void fsl_fdt_fixup_flash(void *fdt)
6766b6b7e8aSAshish Kumar {
6776b6b7e8aSAshish Kumar int offset;
678143af3c6SPankit Garg #ifdef CONFIG_TFABOOT
679143af3c6SPankit Garg u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
680143af3c6SPankit Garg u32 val;
681143af3c6SPankit Garg #endif
6826b6b7e8aSAshish Kumar
6836b6b7e8aSAshish Kumar /*
6846b6b7e8aSAshish Kumar * IFC-NOR and QSPI are muxed on SoC.
6856b6b7e8aSAshish Kumar * So disable IFC node in dts if QSPI is enabled or
6866b6b7e8aSAshish Kumar * disable QSPI node in dts in case QSPI is not enabled.
6876b6b7e8aSAshish Kumar */
6886b6b7e8aSAshish Kumar
689143af3c6SPankit Garg #ifdef CONFIG_TFABOOT
690143af3c6SPankit Garg enum boot_src src = get_boot_src();
691143af3c6SPankit Garg bool disable_ifc = false;
692143af3c6SPankit Garg
693143af3c6SPankit Garg switch (src) {
694143af3c6SPankit Garg case BOOT_SOURCE_IFC_NOR:
695143af3c6SPankit Garg disable_ifc = false;
696143af3c6SPankit Garg break;
697143af3c6SPankit Garg case BOOT_SOURCE_QSPI_NOR:
698143af3c6SPankit Garg disable_ifc = true;
699143af3c6SPankit Garg break;
700143af3c6SPankit Garg default:
701143af3c6SPankit Garg val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
702143af3c6SPankit Garg if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
703143af3c6SPankit Garg disable_ifc = true;
704143af3c6SPankit Garg break;
705143af3c6SPankit Garg }
706143af3c6SPankit Garg
707143af3c6SPankit Garg if (disable_ifc) {
708143af3c6SPankit Garg offset = fdt_path_offset(fdt, "/soc/ifc/nor");
709143af3c6SPankit Garg
710143af3c6SPankit Garg if (offset < 0)
711143af3c6SPankit Garg offset = fdt_path_offset(fdt, "/ifc/nor");
712143af3c6SPankit Garg } else {
713143af3c6SPankit Garg offset = fdt_path_offset(fdt, "/soc/quadspi");
714143af3c6SPankit Garg
715143af3c6SPankit Garg if (offset < 0)
716143af3c6SPankit Garg offset = fdt_path_offset(fdt, "/quadspi");
717143af3c6SPankit Garg }
718143af3c6SPankit Garg
719143af3c6SPankit Garg #else
7206b6b7e8aSAshish Kumar #ifdef CONFIG_FSL_QSPI
7216b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/soc/ifc/nor");
7226b6b7e8aSAshish Kumar
7236b6b7e8aSAshish Kumar if (offset < 0)
7246b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/ifc/nor");
7256b6b7e8aSAshish Kumar #else
7266b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/soc/quadspi");
7276b6b7e8aSAshish Kumar
7286b6b7e8aSAshish Kumar if (offset < 0)
7296b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/quadspi");
7306b6b7e8aSAshish Kumar #endif
731143af3c6SPankit Garg #endif
7326b6b7e8aSAshish Kumar if (offset < 0)
7336b6b7e8aSAshish Kumar return;
7346b6b7e8aSAshish Kumar
7356b6b7e8aSAshish Kumar fdt_status_disabled(fdt, offset);
7366b6b7e8aSAshish Kumar }
7376b6b7e8aSAshish Kumar
ft_board_setup(void * blob,bd_t * bd)738e84a324bSAshish Kumar int ft_board_setup(void *blob, bd_t *bd)
739e84a324bSAshish Kumar {
7404130780aSMian Yousaf Kaukab int i;
741e84a324bSAshish Kumar u64 base[CONFIG_NR_DRAM_BANKS];
742e84a324bSAshish Kumar u64 size[CONFIG_NR_DRAM_BANKS];
743e84a324bSAshish Kumar
744e84a324bSAshish Kumar ft_cpu_setup(blob, bd);
745e84a324bSAshish Kumar
746e84a324bSAshish Kumar /* fixup DT for the two GPP DDR banks */
747e84a324bSAshish Kumar for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
748e84a324bSAshish Kumar base[i] = gd->bd->bi_dram[i].start;
749e84a324bSAshish Kumar size[i] = gd->bd->bi_dram[i].size;
750e84a324bSAshish Kumar }
751e84a324bSAshish Kumar
752e84a324bSAshish Kumar #ifdef CONFIG_RESV_RAM
753e84a324bSAshish Kumar /* reduce size if reserved memory is within this bank */
754e84a324bSAshish Kumar if (gd->arch.resv_ram >= base[0] &&
755e84a324bSAshish Kumar gd->arch.resv_ram < base[0] + size[0])
756e84a324bSAshish Kumar size[0] = gd->arch.resv_ram - base[0];
757e84a324bSAshish Kumar else if (gd->arch.resv_ram >= base[1] &&
758e84a324bSAshish Kumar gd->arch.resv_ram < base[1] + size[1])
759e84a324bSAshish Kumar size[1] = gd->arch.resv_ram - base[1];
760e84a324bSAshish Kumar #endif
761e84a324bSAshish Kumar
762e84a324bSAshish Kumar fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
763e84a324bSAshish Kumar
764a78df40cSNipun Gupta fdt_fsl_mc_fixup_iommu_map_entry(blob);
765a78df40cSNipun Gupta
7666b6b7e8aSAshish Kumar fsl_fdt_fixup_flash(blob);
7676b6b7e8aSAshish Kumar
768e84a324bSAshish Kumar #ifdef CONFIG_FSL_MC_ENET
769e84a324bSAshish Kumar fdt_fixup_board_enet(blob);
770e84a324bSAshish Kumar #endif
7715b595df3SPramod Kumar if (is_pb_board())
7725b595df3SPramod Kumar fixup_ls1088ardb_pb_banner(blob);
773e84a324bSAshish Kumar
774e84a324bSAshish Kumar return 0;
775e84a324bSAshish Kumar }
776e84a324bSAshish Kumar #endif
77710e7eaf0SSumit Garg #endif /* defined(CONFIG_SPL_BUILD) */
778143af3c6SPankit Garg
779143af3c6SPankit Garg #ifdef CONFIG_TFABOOT
780143af3c6SPankit Garg #ifdef CONFIG_MTD_NOR_FLASH
is_flash_available(void)781143af3c6SPankit Garg int is_flash_available(void)
782143af3c6SPankit Garg {
783143af3c6SPankit Garg char *env_hwconfig = env_get("hwconfig");
784143af3c6SPankit Garg enum boot_src src = get_boot_src();
785143af3c6SPankit Garg int is_nor_flash_available = 1;
786143af3c6SPankit Garg
787143af3c6SPankit Garg switch (src) {
788143af3c6SPankit Garg case BOOT_SOURCE_IFC_NOR:
789143af3c6SPankit Garg is_nor_flash_available = 1;
790143af3c6SPankit Garg break;
791143af3c6SPankit Garg case BOOT_SOURCE_QSPI_NOR:
792143af3c6SPankit Garg is_nor_flash_available = 0;
793143af3c6SPankit Garg break;
794143af3c6SPankit Garg /*
795143af3c6SPankit Garg * In Case of SD boot,if qspi is defined in env_hwconfig
796143af3c6SPankit Garg * disable nor flash probe.
797143af3c6SPankit Garg */
798143af3c6SPankit Garg default:
799143af3c6SPankit Garg if (hwconfig_f("qspi", env_hwconfig))
800143af3c6SPankit Garg is_nor_flash_available = 0;
801143af3c6SPankit Garg break;
802143af3c6SPankit Garg }
803143af3c6SPankit Garg return is_nor_flash_available;
804143af3c6SPankit Garg }
805143af3c6SPankit Garg #endif
806143af3c6SPankit Garg
env_sf_get_env_addr(void)807143af3c6SPankit Garg void *env_sf_get_env_addr(void)
808143af3c6SPankit Garg {
809143af3c6SPankit Garg return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
810143af3c6SPankit Garg }
811143af3c6SPankit Garg #endif
812