183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2e84a324bSAshish Kumar /* 3*5b595df3SPramod Kumar * Copyright 2017-2018 NXP 4e84a324bSAshish Kumar */ 5e84a324bSAshish Kumar #include <common.h> 6e84a324bSAshish Kumar #include <i2c.h> 7e84a324bSAshish Kumar #include <malloc.h> 8e84a324bSAshish Kumar #include <errno.h> 9e84a324bSAshish Kumar #include <netdev.h> 10e84a324bSAshish Kumar #include <fsl_ifc.h> 11e84a324bSAshish Kumar #include <fsl_ddr.h> 12e84a324bSAshish Kumar #include <fsl_sec.h> 13e84a324bSAshish Kumar #include <asm/io.h> 14e84a324bSAshish Kumar #include <fdt_support.h> 15b08c8c48SMasahiro Yamada #include <linux/libfdt.h> 16e84a324bSAshish Kumar #include <fsl-mc/fsl_mc.h> 17e84a324bSAshish Kumar #include <environment.h> 18e84a324bSAshish Kumar #include <asm/arch-fsl-layerscape/soc.h> 19e84a324bSAshish Kumar #include <asm/arch/ppa.h> 2044cdb5b6SYangbo Lu #include <hwconfig.h> 21ef0789b7SRajesh Bhagat #include <asm/arch/fsl_serdes.h> 22ef0789b7SRajesh Bhagat #include <asm/arch/soc.h> 23e84a324bSAshish Kumar 24e84a324bSAshish Kumar #include "../common/qixis.h" 25e84a324bSAshish Kumar #include "ls1088a_qixis.h" 26ef0789b7SRajesh Bhagat #include "../common/vid.h" 27ef0789b7SRajesh Bhagat #include <fsl_immap.h> 28e84a324bSAshish Kumar 29e84a324bSAshish Kumar DECLARE_GLOBAL_DATA_PTR; 30e84a324bSAshish Kumar 3110e7eaf0SSumit Garg int board_early_init_f(void) 3210e7eaf0SSumit Garg { 33169d493bSAshish Kumar #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS) 34169d493bSAshish Kumar i2c_early_init_f(); 35169d493bSAshish Kumar #endif 3610e7eaf0SSumit Garg fsl_lsch3_early_init_f(); 3710e7eaf0SSumit Garg return 0; 3810e7eaf0SSumit Garg } 3910e7eaf0SSumit Garg 4010e7eaf0SSumit Garg #ifdef CONFIG_FSL_QIXIS 41e84a324bSAshish Kumar unsigned long long get_qixis_addr(void) 42e84a324bSAshish Kumar { 43e84a324bSAshish Kumar unsigned long long addr; 44e84a324bSAshish Kumar 45e84a324bSAshish Kumar if (gd->flags & GD_FLG_RELOC) 46e84a324bSAshish Kumar addr = QIXIS_BASE_PHYS; 47e84a324bSAshish Kumar else 48e84a324bSAshish Kumar addr = QIXIS_BASE_PHYS_EARLY; 49e84a324bSAshish Kumar 50e84a324bSAshish Kumar /* 51e84a324bSAshish Kumar * IFC address under 256MB is mapped to 0x30000000, any address above 52e84a324bSAshish Kumar * is mapped to 0x5_10000000 up to 4GB. 53e84a324bSAshish Kumar */ 54e84a324bSAshish Kumar addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; 55e84a324bSAshish Kumar 56e84a324bSAshish Kumar return addr; 57e84a324bSAshish Kumar } 5810e7eaf0SSumit Garg #endif 59e84a324bSAshish Kumar 60ef0789b7SRajesh Bhagat #if defined(CONFIG_VID) 61ef0789b7SRajesh Bhagat int init_func_vid(void) 62ef0789b7SRajesh Bhagat { 63ef0789b7SRajesh Bhagat if (adjust_vdd(0) < 0) 64ef0789b7SRajesh Bhagat printf("core voltage not adjusted\n"); 65ef0789b7SRajesh Bhagat 66ef0789b7SRajesh Bhagat return 0; 67ef0789b7SRajesh Bhagat } 68ef0789b7SRajesh Bhagat #endif 69ef0789b7SRajesh Bhagat 70*5b595df3SPramod Kumar int is_pb_board(void) 71*5b595df3SPramod Kumar { 72*5b595df3SPramod Kumar u8 board_id; 73*5b595df3SPramod Kumar 74*5b595df3SPramod Kumar board_id = QIXIS_READ(id); 75*5b595df3SPramod Kumar if (board_id == LS1088ARDB_PB_BOARD) 76*5b595df3SPramod Kumar return 1; 77*5b595df3SPramod Kumar else 78*5b595df3SPramod Kumar return 0; 79*5b595df3SPramod Kumar } 80*5b595df3SPramod Kumar 81*5b595df3SPramod Kumar int fixup_ls1088ardb_pb_banner(void *fdt) 82*5b595df3SPramod Kumar { 83*5b595df3SPramod Kumar fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board"); 84*5b595df3SPramod Kumar 85*5b595df3SPramod Kumar return 0; 86*5b595df3SPramod Kumar } 87*5b595df3SPramod Kumar 8810e7eaf0SSumit Garg #if !defined(CONFIG_SPL_BUILD) 89e84a324bSAshish Kumar int checkboard(void) 90e84a324bSAshish Kumar { 91e84a324bSAshish Kumar char buf[64]; 92e84a324bSAshish Kumar u8 sw; 93e84a324bSAshish Kumar static const char *const freq[] = {"100", "125", "156.25", 94e84a324bSAshish Kumar "100 separate SSCG"}; 95e84a324bSAshish Kumar int clock; 96e84a324bSAshish Kumar 977769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 987769776aSAshish Kumar printf("Board: LS1088A-QDS, "); 997769776aSAshish Kumar #else 100*5b595df3SPramod Kumar if (is_pb_board()) 101*5b595df3SPramod Kumar printf("Board: LS1088ARDB-PB, "); 102*5b595df3SPramod Kumar else 103e84a324bSAshish Kumar printf("Board: LS1088A-RDB, "); 1047769776aSAshish Kumar #endif 105e84a324bSAshish Kumar 106e84a324bSAshish Kumar sw = QIXIS_READ(arch); 107e84a324bSAshish Kumar printf("Board Arch: V%d, ", sw >> 4); 108e84a324bSAshish Kumar 1097769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 1107769776aSAshish Kumar printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); 1117769776aSAshish Kumar #else 112e84a324bSAshish Kumar printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); 1137769776aSAshish Kumar #endif 114e84a324bSAshish Kumar 115e84a324bSAshish Kumar memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); 116e84a324bSAshish Kumar 117e84a324bSAshish Kumar sw = QIXIS_READ(brdcfg[0]); 118e84a324bSAshish Kumar sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 119e84a324bSAshish Kumar 120e84a324bSAshish Kumar #ifdef CONFIG_SD_BOOT 121e84a324bSAshish Kumar puts("SD card\n"); 122e84a324bSAshish Kumar #endif 123e84a324bSAshish Kumar switch (sw) { 1247769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 125e84a324bSAshish Kumar case 0: 1267769776aSAshish Kumar case 1: 1277769776aSAshish Kumar case 2: 1287769776aSAshish Kumar case 3: 1297769776aSAshish Kumar case 4: 1307769776aSAshish Kumar case 5: 1317769776aSAshish Kumar case 6: 1327769776aSAshish Kumar case 7: 1337769776aSAshish Kumar printf("vBank: %d\n", sw); 1347769776aSAshish Kumar break; 1357769776aSAshish Kumar case 8: 1367769776aSAshish Kumar puts("PromJet\n"); 1377769776aSAshish Kumar break; 1387769776aSAshish Kumar case 15: 1397769776aSAshish Kumar puts("IFCCard\n"); 1407769776aSAshish Kumar break; 1417769776aSAshish Kumar case 14: 1427769776aSAshish Kumar #else 1437769776aSAshish Kumar case 0: 1447769776aSAshish Kumar #endif 145e84a324bSAshish Kumar puts("QSPI:"); 146e84a324bSAshish Kumar sw = QIXIS_READ(brdcfg[0]); 147e84a324bSAshish Kumar sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT; 148e84a324bSAshish Kumar if (sw == 0 || sw == 4) 149e84a324bSAshish Kumar puts("0\n"); 150e84a324bSAshish Kumar else if (sw == 1) 151e84a324bSAshish Kumar puts("1\n"); 152e84a324bSAshish Kumar else 153e84a324bSAshish Kumar puts("EMU\n"); 154e84a324bSAshish Kumar break; 155e84a324bSAshish Kumar 156e84a324bSAshish Kumar default: 157e84a324bSAshish Kumar printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 158e84a324bSAshish Kumar break; 159e84a324bSAshish Kumar } 160e84a324bSAshish Kumar 1617769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 1627769776aSAshish Kumar printf("FPGA: v%d (%s), build %d", 1637769776aSAshish Kumar (int)QIXIS_READ(scver), qixis_read_tag(buf), 1647769776aSAshish Kumar (int)qixis_read_minor()); 1657769776aSAshish Kumar /* the timestamp string contains "\n" at the end */ 1667769776aSAshish Kumar printf(" on %s", qixis_read_time(buf)); 1677769776aSAshish Kumar #else 168e84a324bSAshish Kumar printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); 1697769776aSAshish Kumar #endif 170e84a324bSAshish Kumar 171e84a324bSAshish Kumar /* 172e84a324bSAshish Kumar * Display the actual SERDES reference clocks as configured by the 173e84a324bSAshish Kumar * dip switches on the board. Note that the SWx registers could 174e84a324bSAshish Kumar * technically be set to force the reference clocks to match the 175e84a324bSAshish Kumar * values that the SERDES expects (or vice versa). For now, however, 176e84a324bSAshish Kumar * we just display both values and hope the user notices when they 177e84a324bSAshish Kumar * don't match. 178e84a324bSAshish Kumar */ 179e84a324bSAshish Kumar puts("SERDES1 Reference : "); 180e84a324bSAshish Kumar sw = QIXIS_READ(brdcfg[2]); 181e84a324bSAshish Kumar clock = (sw >> 6) & 3; 182e84a324bSAshish Kumar printf("Clock1 = %sMHz ", freq[clock]); 183e84a324bSAshish Kumar clock = (sw >> 4) & 3; 184e84a324bSAshish Kumar printf("Clock2 = %sMHz", freq[clock]); 185e84a324bSAshish Kumar 186e84a324bSAshish Kumar puts("\nSERDES2 Reference : "); 187e84a324bSAshish Kumar clock = (sw >> 2) & 3; 188e84a324bSAshish Kumar printf("Clock1 = %sMHz ", freq[clock]); 189e84a324bSAshish Kumar clock = (sw >> 0) & 3; 190e84a324bSAshish Kumar printf("Clock2 = %sMHz\n", freq[clock]); 191e84a324bSAshish Kumar 192e84a324bSAshish Kumar return 0; 193e84a324bSAshish Kumar } 194d12b166aSAshish Kumar #endif 195e84a324bSAshish Kumar 196e84a324bSAshish Kumar bool if_board_diff_clk(void) 197e84a324bSAshish Kumar { 1987769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 1997769776aSAshish Kumar u8 diff_conf = QIXIS_READ(brdcfg[11]); 2007769776aSAshish Kumar return diff_conf & 0x40; 2017769776aSAshish Kumar #else 202e84a324bSAshish Kumar u8 diff_conf = QIXIS_READ(dutcfg[11]); 203e84a324bSAshish Kumar return diff_conf & 0x80; 2047769776aSAshish Kumar #endif 205e84a324bSAshish Kumar } 206e84a324bSAshish Kumar 207e84a324bSAshish Kumar unsigned long get_board_sys_clk(void) 208e84a324bSAshish Kumar { 209e84a324bSAshish Kumar u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 210e84a324bSAshish Kumar 211e84a324bSAshish Kumar switch (sysclk_conf & 0x0f) { 212e84a324bSAshish Kumar case QIXIS_SYSCLK_83: 213e84a324bSAshish Kumar return 83333333; 214e84a324bSAshish Kumar case QIXIS_SYSCLK_100: 215e84a324bSAshish Kumar return 100000000; 216e84a324bSAshish Kumar case QIXIS_SYSCLK_125: 217e84a324bSAshish Kumar return 125000000; 218e84a324bSAshish Kumar case QIXIS_SYSCLK_133: 219e84a324bSAshish Kumar return 133333333; 220e84a324bSAshish Kumar case QIXIS_SYSCLK_150: 221e84a324bSAshish Kumar return 150000000; 222e84a324bSAshish Kumar case QIXIS_SYSCLK_160: 223e84a324bSAshish Kumar return 160000000; 224e84a324bSAshish Kumar case QIXIS_SYSCLK_166: 225e84a324bSAshish Kumar return 166666666; 226e84a324bSAshish Kumar } 227e84a324bSAshish Kumar 228e84a324bSAshish Kumar return 66666666; 229e84a324bSAshish Kumar } 230e84a324bSAshish Kumar 231e84a324bSAshish Kumar unsigned long get_board_ddr_clk(void) 232e84a324bSAshish Kumar { 233e84a324bSAshish Kumar u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 234e84a324bSAshish Kumar 235e84a324bSAshish Kumar if (if_board_diff_clk()) 236e84a324bSAshish Kumar return get_board_sys_clk(); 237e84a324bSAshish Kumar switch ((ddrclk_conf & 0x30) >> 4) { 238e84a324bSAshish Kumar case QIXIS_DDRCLK_100: 239e84a324bSAshish Kumar return 100000000; 240e84a324bSAshish Kumar case QIXIS_DDRCLK_125: 241e84a324bSAshish Kumar return 125000000; 242e84a324bSAshish Kumar case QIXIS_DDRCLK_133: 243e84a324bSAshish Kumar return 133333333; 244e84a324bSAshish Kumar } 245e84a324bSAshish Kumar 246e84a324bSAshish Kumar return 66666666; 247e84a324bSAshish Kumar } 248e84a324bSAshish Kumar 249e84a324bSAshish Kumar int select_i2c_ch_pca9547(u8 ch) 250e84a324bSAshish Kumar { 251e84a324bSAshish Kumar int ret; 252e84a324bSAshish Kumar 253e84a324bSAshish Kumar ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 254e84a324bSAshish Kumar if (ret) { 255e84a324bSAshish Kumar puts("PCA: failed to select proper channel\n"); 256e84a324bSAshish Kumar return ret; 257e84a324bSAshish Kumar } 258e84a324bSAshish Kumar 259e84a324bSAshish Kumar return 0; 260e84a324bSAshish Kumar } 261e84a324bSAshish Kumar 262980d61a2SRajesh Bhagat #if !defined(CONFIG_SPL_BUILD) 263e84a324bSAshish Kumar void board_retimer_init(void) 264e84a324bSAshish Kumar { 265e84a324bSAshish Kumar u8 reg; 266e84a324bSAshish Kumar 267e84a324bSAshish Kumar /* Retimer is connected to I2C1_CH5 */ 268e84a324bSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH5); 269e84a324bSAshish Kumar 270e84a324bSAshish Kumar /* Access to Control/Shared register */ 271e84a324bSAshish Kumar reg = 0x0; 272e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 273e84a324bSAshish Kumar 274e84a324bSAshish Kumar /* Read device revision and ID */ 275e84a324bSAshish Kumar i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); 276e84a324bSAshish Kumar debug("Retimer version id = 0x%x\n", reg); 277e84a324bSAshish Kumar 278e84a324bSAshish Kumar /* Enable Broadcast. All writes target all channel register sets */ 279e84a324bSAshish Kumar reg = 0x0c; 280e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 281e84a324bSAshish Kumar 282e84a324bSAshish Kumar /* Reset Channel Registers */ 283e84a324bSAshish Kumar i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); 284e84a324bSAshish Kumar reg |= 0x4; 285e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); 286e84a324bSAshish Kumar 287e84a324bSAshish Kumar /* Set data rate as 10.3125 Gbps */ 288e84a324bSAshish Kumar reg = 0x90; 289e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); 290e84a324bSAshish Kumar reg = 0xb3; 291e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); 292e84a324bSAshish Kumar reg = 0x90; 293e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); 294e84a324bSAshish Kumar reg = 0xb3; 295e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); 296e84a324bSAshish Kumar reg = 0xcd; 297e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); 298e84a324bSAshish Kumar 299e84a324bSAshish Kumar /* Select VCO Divider to full rate (000) */ 300e84a324bSAshish Kumar i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); 301e84a324bSAshish Kumar reg &= 0x0f; 302e84a324bSAshish Kumar reg |= 0x70; 303e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); 304e84a324bSAshish Kumar 3057769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 3067769776aSAshish Kumar /* Retimer is connected to I2C1_CH5 */ 3077769776aSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH5); 308e84a324bSAshish Kumar 3097769776aSAshish Kumar /* Access to Control/Shared register */ 3107769776aSAshish Kumar reg = 0x0; 3117769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); 3127769776aSAshish Kumar 3137769776aSAshish Kumar /* Read device revision and ID */ 3147769776aSAshish Kumar i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1); 3157769776aSAshish Kumar debug("Retimer version id = 0x%x\n", reg); 3167769776aSAshish Kumar 3177769776aSAshish Kumar /* Enable Broadcast. All writes target all channel register sets */ 3187769776aSAshish Kumar reg = 0x0c; 3197769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); 3207769776aSAshish Kumar 3217769776aSAshish Kumar /* Reset Channel Registers */ 3227769776aSAshish Kumar i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1); 3237769776aSAshish Kumar reg |= 0x4; 3247769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1); 3257769776aSAshish Kumar 3267769776aSAshish Kumar /* Set data rate as 10.3125 Gbps */ 3277769776aSAshish Kumar reg = 0x90; 3287769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1); 3297769776aSAshish Kumar reg = 0xb3; 3307769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1); 3317769776aSAshish Kumar reg = 0x90; 3327769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1); 3337769776aSAshish Kumar reg = 0xb3; 3347769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1); 3357769776aSAshish Kumar reg = 0xcd; 3367769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1); 3377769776aSAshish Kumar 3387769776aSAshish Kumar /* Select VCO Divider to full rate (000) */ 3397769776aSAshish Kumar i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); 3407769776aSAshish Kumar reg &= 0x0f; 3417769776aSAshish Kumar reg |= 0x70; 3427769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); 3437769776aSAshish Kumar #endif 344e84a324bSAshish Kumar /*return the default channel*/ 345e84a324bSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 346e84a324bSAshish Kumar } 347e84a324bSAshish Kumar 34844cdb5b6SYangbo Lu #ifdef CONFIG_MISC_INIT_R 34944cdb5b6SYangbo Lu int misc_init_r(void) 35044cdb5b6SYangbo Lu { 35144cdb5b6SYangbo Lu #ifdef CONFIG_TARGET_LS1088ARDB 35244cdb5b6SYangbo Lu u8 brdcfg5; 35344cdb5b6SYangbo Lu 35444cdb5b6SYangbo Lu if (hwconfig("esdhc-force-sd")) { 35544cdb5b6SYangbo Lu brdcfg5 = QIXIS_READ(brdcfg[5]); 35644cdb5b6SYangbo Lu brdcfg5 &= ~BRDCFG5_SPISDHC_MASK; 35744cdb5b6SYangbo Lu brdcfg5 |= BRDCFG5_FORCE_SD; 35844cdb5b6SYangbo Lu QIXIS_WRITE(brdcfg[5], brdcfg5); 35944cdb5b6SYangbo Lu } 36044cdb5b6SYangbo Lu #endif 36144cdb5b6SYangbo Lu return 0; 36244cdb5b6SYangbo Lu } 36344cdb5b6SYangbo Lu #endif 364980d61a2SRajesh Bhagat #endif 36544cdb5b6SYangbo Lu 366ef0789b7SRajesh Bhagat int i2c_multiplexer_select_vid_channel(u8 channel) 367ef0789b7SRajesh Bhagat { 368ef0789b7SRajesh Bhagat return select_i2c_ch_pca9547(channel); 369ef0789b7SRajesh Bhagat } 370ef0789b7SRajesh Bhagat 371ef0789b7SRajesh Bhagat #ifdef CONFIG_TARGET_LS1088AQDS 372ef0789b7SRajesh Bhagat /* read the current value(SVDD) of the LTM Regulator Voltage */ 373ef0789b7SRajesh Bhagat int get_serdes_volt(void) 374ef0789b7SRajesh Bhagat { 375ef0789b7SRajesh Bhagat int ret, vcode = 0; 376ef0789b7SRajesh Bhagat u8 chan = PWM_CHANNEL0; 377ef0789b7SRajesh Bhagat 378ef0789b7SRajesh Bhagat /* Select the PAGE 0 using PMBus commands PAGE for VDD */ 379ef0789b7SRajesh Bhagat ret = i2c_write(I2C_SVDD_MONITOR_ADDR, 380ef0789b7SRajesh Bhagat PMBUS_CMD_PAGE, 1, &chan, 1); 381ef0789b7SRajesh Bhagat if (ret) { 382ef0789b7SRajesh Bhagat printf("VID: failed to select VDD Page 0\n"); 383ef0789b7SRajesh Bhagat return ret; 384ef0789b7SRajesh Bhagat } 385ef0789b7SRajesh Bhagat 386ef0789b7SRajesh Bhagat /* Read the output voltage using PMBus command READ_VOUT */ 387ef0789b7SRajesh Bhagat ret = i2c_read(I2C_SVDD_MONITOR_ADDR, 388ef0789b7SRajesh Bhagat PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); 389ef0789b7SRajesh Bhagat if (ret) { 390ef0789b7SRajesh Bhagat printf("VID: failed to read the volatge\n"); 391ef0789b7SRajesh Bhagat return ret; 392ef0789b7SRajesh Bhagat } 393ef0789b7SRajesh Bhagat 394ef0789b7SRajesh Bhagat return vcode; 395ef0789b7SRajesh Bhagat } 396ef0789b7SRajesh Bhagat 397ef0789b7SRajesh Bhagat int set_serdes_volt(int svdd) 398ef0789b7SRajesh Bhagat { 399ef0789b7SRajesh Bhagat int ret, vdd_last; 400ef0789b7SRajesh Bhagat u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, 401ef0789b7SRajesh Bhagat svdd & 0xFF, (svdd & 0xFF00) >> 8}; 402ef0789b7SRajesh Bhagat 403ef0789b7SRajesh Bhagat /* Write the desired voltage code to the SVDD regulator */ 404ef0789b7SRajesh Bhagat ret = i2c_write(I2C_SVDD_MONITOR_ADDR, 405ef0789b7SRajesh Bhagat PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); 406ef0789b7SRajesh Bhagat if (ret) { 407ef0789b7SRajesh Bhagat printf("VID: I2C failed to write to the volatge regulator\n"); 408ef0789b7SRajesh Bhagat return -1; 409ef0789b7SRajesh Bhagat } 410ef0789b7SRajesh Bhagat 411ef0789b7SRajesh Bhagat /* Wait for the volatge to get to the desired value */ 412ef0789b7SRajesh Bhagat do { 413ef0789b7SRajesh Bhagat vdd_last = get_serdes_volt(); 414ef0789b7SRajesh Bhagat if (vdd_last < 0) { 415ef0789b7SRajesh Bhagat printf("VID: Couldn't read sensor abort VID adjust\n"); 416ef0789b7SRajesh Bhagat return -1; 417ef0789b7SRajesh Bhagat } 418ef0789b7SRajesh Bhagat } while (vdd_last != svdd); 419ef0789b7SRajesh Bhagat 420ef0789b7SRajesh Bhagat return 1; 421ef0789b7SRajesh Bhagat } 422ef0789b7SRajesh Bhagat #else 423ef0789b7SRajesh Bhagat int get_serdes_volt(void) 424ef0789b7SRajesh Bhagat { 425ef0789b7SRajesh Bhagat return 0; 426ef0789b7SRajesh Bhagat } 427ef0789b7SRajesh Bhagat 428ef0789b7SRajesh Bhagat int set_serdes_volt(int svdd) 429ef0789b7SRajesh Bhagat { 430ef0789b7SRajesh Bhagat int ret; 431ef0789b7SRajesh Bhagat u8 brdcfg4; 432ef0789b7SRajesh Bhagat 433ef0789b7SRajesh Bhagat printf("SVDD changing of RDB\n"); 434ef0789b7SRajesh Bhagat 435ef0789b7SRajesh Bhagat /* Read the BRDCFG54 via CLPD */ 436ef0789b7SRajesh Bhagat ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR, 437ef0789b7SRajesh Bhagat QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); 438ef0789b7SRajesh Bhagat if (ret) { 439ef0789b7SRajesh Bhagat printf("VID: I2C failed to read the CPLD BRDCFG4\n"); 440ef0789b7SRajesh Bhagat return -1; 441ef0789b7SRajesh Bhagat } 442ef0789b7SRajesh Bhagat 443ef0789b7SRajesh Bhagat brdcfg4 = brdcfg4 | 0x08; 444ef0789b7SRajesh Bhagat 445ef0789b7SRajesh Bhagat /* Write to the BRDCFG4 */ 446ef0789b7SRajesh Bhagat ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 447ef0789b7SRajesh Bhagat QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); 448ef0789b7SRajesh Bhagat if (ret) { 449ef0789b7SRajesh Bhagat debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n"); 450ef0789b7SRajesh Bhagat return -1; 451ef0789b7SRajesh Bhagat } 452ef0789b7SRajesh Bhagat 453ef0789b7SRajesh Bhagat /* Wait for the volatge to get to the desired value */ 454ef0789b7SRajesh Bhagat udelay(10000); 455ef0789b7SRajesh Bhagat 456ef0789b7SRajesh Bhagat return 1; 457ef0789b7SRajesh Bhagat } 458ef0789b7SRajesh Bhagat #endif 459ef0789b7SRajesh Bhagat 460ef0789b7SRajesh Bhagat /* this function disables the SERDES, changes the SVDD Voltage and enables it*/ 461ef0789b7SRajesh Bhagat int board_adjust_vdd(int vdd) 462ef0789b7SRajesh Bhagat { 463ef0789b7SRajesh Bhagat int ret = 0; 464ef0789b7SRajesh Bhagat 465ef0789b7SRajesh Bhagat debug("%s: vdd = %d\n", __func__, vdd); 466ef0789b7SRajesh Bhagat 467ef0789b7SRajesh Bhagat /* Special settings to be performed when voltage is 900mV */ 468ef0789b7SRajesh Bhagat if (vdd == 900) { 469ef0789b7SRajesh Bhagat ret = setup_serdes_volt(vdd); 470ef0789b7SRajesh Bhagat if (ret < 0) { 471ef0789b7SRajesh Bhagat ret = -1; 472ef0789b7SRajesh Bhagat goto exit; 473ef0789b7SRajesh Bhagat } 474ef0789b7SRajesh Bhagat } 475ef0789b7SRajesh Bhagat exit: 476ef0789b7SRajesh Bhagat return ret; 477ef0789b7SRajesh Bhagat } 478ef0789b7SRajesh Bhagat 479980d61a2SRajesh Bhagat #if !defined(CONFIG_SPL_BUILD) 480e84a324bSAshish Kumar int board_init(void) 481e84a324bSAshish Kumar { 482e84a324bSAshish Kumar init_final_memctl_regs(); 483e84a324bSAshish Kumar #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) 484e84a324bSAshish Kumar u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; 485e84a324bSAshish Kumar #endif 486e84a324bSAshish Kumar 487e84a324bSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 488e84a324bSAshish Kumar board_retimer_init(); 489e84a324bSAshish Kumar 490e84a324bSAshish Kumar #ifdef CONFIG_ENV_IS_NOWHERE 491e84a324bSAshish Kumar gd->env_addr = (ulong)&default_environment[0]; 492e84a324bSAshish Kumar #endif 493e84a324bSAshish Kumar 494e84a324bSAshish Kumar #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) 495e84a324bSAshish Kumar /* invert AQR105 IRQ pins polarity */ 496e84a324bSAshish Kumar out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK); 497e84a324bSAshish Kumar #endif 498e84a324bSAshish Kumar 49930c41d21SUdit Agarwal #ifdef CONFIG_FSL_CAAM 50030c41d21SUdit Agarwal sec_init(); 50130c41d21SUdit Agarwal #endif 502e84a324bSAshish Kumar #ifdef CONFIG_FSL_LS_PPA 503e84a324bSAshish Kumar ppa_init(); 504e84a324bSAshish Kumar #endif 505e84a324bSAshish Kumar return 0; 506e84a324bSAshish Kumar } 507e84a324bSAshish Kumar 508e84a324bSAshish Kumar void detail_board_ddr_info(void) 509e84a324bSAshish Kumar { 510e84a324bSAshish Kumar puts("\nDDR "); 511e84a324bSAshish Kumar print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); 512e84a324bSAshish Kumar print_ddr_info(0); 513e84a324bSAshish Kumar } 514e84a324bSAshish Kumar 515e84a324bSAshish Kumar #if defined(CONFIG_ARCH_MISC_INIT) 516e84a324bSAshish Kumar int arch_misc_init(void) 517e84a324bSAshish Kumar { 518e84a324bSAshish Kumar return 0; 519e84a324bSAshish Kumar } 520e84a324bSAshish Kumar #endif 521e84a324bSAshish Kumar 522e84a324bSAshish Kumar #ifdef CONFIG_FSL_MC_ENET 523e84a324bSAshish Kumar void fdt_fixup_board_enet(void *fdt) 524e84a324bSAshish Kumar { 525e84a324bSAshish Kumar int offset; 526e84a324bSAshish Kumar 527e84a324bSAshish Kumar offset = fdt_path_offset(fdt, "/fsl-mc"); 528e84a324bSAshish Kumar 529e84a324bSAshish Kumar if (offset < 0) 530e84a324bSAshish Kumar offset = fdt_path_offset(fdt, "/fsl,dprc@0"); 531e84a324bSAshish Kumar 532e84a324bSAshish Kumar if (offset < 0) { 533e84a324bSAshish Kumar printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", 534e84a324bSAshish Kumar __func__, offset); 535e84a324bSAshish Kumar return; 536e84a324bSAshish Kumar } 537e84a324bSAshish Kumar 53870a131ebSYogesh Gaur if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) 539e84a324bSAshish Kumar fdt_status_okay(fdt, offset); 540e84a324bSAshish Kumar else 541e84a324bSAshish Kumar fdt_status_fail(fdt, offset); 542e84a324bSAshish Kumar } 543e84a324bSAshish Kumar #endif 544e84a324bSAshish Kumar 545e84a324bSAshish Kumar #ifdef CONFIG_OF_BOARD_SETUP 5466b6b7e8aSAshish Kumar void fsl_fdt_fixup_flash(void *fdt) 5476b6b7e8aSAshish Kumar { 5486b6b7e8aSAshish Kumar int offset; 5496b6b7e8aSAshish Kumar 5506b6b7e8aSAshish Kumar /* 5516b6b7e8aSAshish Kumar * IFC-NOR and QSPI are muxed on SoC. 5526b6b7e8aSAshish Kumar * So disable IFC node in dts if QSPI is enabled or 5536b6b7e8aSAshish Kumar * disable QSPI node in dts in case QSPI is not enabled. 5546b6b7e8aSAshish Kumar */ 5556b6b7e8aSAshish Kumar 5566b6b7e8aSAshish Kumar #ifdef CONFIG_FSL_QSPI 5576b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/soc/ifc/nor"); 5586b6b7e8aSAshish Kumar 5596b6b7e8aSAshish Kumar if (offset < 0) 5606b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/ifc/nor"); 5616b6b7e8aSAshish Kumar #else 5626b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/soc/quadspi"); 5636b6b7e8aSAshish Kumar 5646b6b7e8aSAshish Kumar if (offset < 0) 5656b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/quadspi"); 5666b6b7e8aSAshish Kumar #endif 5676b6b7e8aSAshish Kumar if (offset < 0) 5686b6b7e8aSAshish Kumar return; 5696b6b7e8aSAshish Kumar 5706b6b7e8aSAshish Kumar fdt_status_disabled(fdt, offset); 5716b6b7e8aSAshish Kumar } 5726b6b7e8aSAshish Kumar 573e84a324bSAshish Kumar int ft_board_setup(void *blob, bd_t *bd) 574e84a324bSAshish Kumar { 575e84a324bSAshish Kumar int err, i; 576e84a324bSAshish Kumar u64 base[CONFIG_NR_DRAM_BANKS]; 577e84a324bSAshish Kumar u64 size[CONFIG_NR_DRAM_BANKS]; 578e84a324bSAshish Kumar 579e84a324bSAshish Kumar ft_cpu_setup(blob, bd); 580e84a324bSAshish Kumar 581e84a324bSAshish Kumar /* fixup DT for the two GPP DDR banks */ 582e84a324bSAshish Kumar for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 583e84a324bSAshish Kumar base[i] = gd->bd->bi_dram[i].start; 584e84a324bSAshish Kumar size[i] = gd->bd->bi_dram[i].size; 585e84a324bSAshish Kumar } 586e84a324bSAshish Kumar 587e84a324bSAshish Kumar #ifdef CONFIG_RESV_RAM 588e84a324bSAshish Kumar /* reduce size if reserved memory is within this bank */ 589e84a324bSAshish Kumar if (gd->arch.resv_ram >= base[0] && 590e84a324bSAshish Kumar gd->arch.resv_ram < base[0] + size[0]) 591e84a324bSAshish Kumar size[0] = gd->arch.resv_ram - base[0]; 592e84a324bSAshish Kumar else if (gd->arch.resv_ram >= base[1] && 593e84a324bSAshish Kumar gd->arch.resv_ram < base[1] + size[1]) 594e84a324bSAshish Kumar size[1] = gd->arch.resv_ram - base[1]; 595e84a324bSAshish Kumar #endif 596e84a324bSAshish Kumar 597e84a324bSAshish Kumar fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); 598e84a324bSAshish Kumar 599a78df40cSNipun Gupta fdt_fsl_mc_fixup_iommu_map_entry(blob); 600a78df40cSNipun Gupta 6016b6b7e8aSAshish Kumar fsl_fdt_fixup_flash(blob); 6026b6b7e8aSAshish Kumar 603e84a324bSAshish Kumar #ifdef CONFIG_FSL_MC_ENET 604e84a324bSAshish Kumar fdt_fixup_board_enet(blob); 605e84a324bSAshish Kumar err = fsl_mc_ldpaa_exit(bd); 606e84a324bSAshish Kumar if (err) 607e84a324bSAshish Kumar return err; 608e84a324bSAshish Kumar #endif 609*5b595df3SPramod Kumar if (is_pb_board()) 610*5b595df3SPramod Kumar fixup_ls1088ardb_pb_banner(blob); 611e84a324bSAshish Kumar 612e84a324bSAshish Kumar return 0; 613e84a324bSAshish Kumar } 614e84a324bSAshish Kumar #endif 61510e7eaf0SSumit Garg #endif /* defined(CONFIG_SPL_BUILD) */ 616