1e84a324bSAshish Kumar /* 2e84a324bSAshish Kumar * Copyright 2017 NXP 3e84a324bSAshish Kumar * 4e84a324bSAshish Kumar * SPDX-License-Identifier: GPL-2.0+ 5e84a324bSAshish Kumar */ 6e84a324bSAshish Kumar #include <common.h> 7e84a324bSAshish Kumar #include <i2c.h> 8e84a324bSAshish Kumar #include <malloc.h> 9e84a324bSAshish Kumar #include <errno.h> 10e84a324bSAshish Kumar #include <netdev.h> 11e84a324bSAshish Kumar #include <fsl_ifc.h> 12e84a324bSAshish Kumar #include <fsl_ddr.h> 13e84a324bSAshish Kumar #include <fsl_sec.h> 14e84a324bSAshish Kumar #include <asm/io.h> 15e84a324bSAshish Kumar #include <fdt_support.h> 16e84a324bSAshish Kumar #include <libfdt.h> 17e84a324bSAshish Kumar #include <fsl-mc/fsl_mc.h> 18e84a324bSAshish Kumar #include <environment.h> 19e84a324bSAshish Kumar #include <asm/arch-fsl-layerscape/soc.h> 20e84a324bSAshish Kumar #include <asm/arch/ppa.h> 21*44cdb5b6SYangbo Lu #include <hwconfig.h> 22e84a324bSAshish Kumar 23e84a324bSAshish Kumar #include "../common/qixis.h" 24e84a324bSAshish Kumar #include "ls1088a_qixis.h" 25e84a324bSAshish Kumar 26e84a324bSAshish Kumar DECLARE_GLOBAL_DATA_PTR; 27e84a324bSAshish Kumar 28e84a324bSAshish Kumar unsigned long long get_qixis_addr(void) 29e84a324bSAshish Kumar { 30e84a324bSAshish Kumar unsigned long long addr; 31e84a324bSAshish Kumar 32e84a324bSAshish Kumar if (gd->flags & GD_FLG_RELOC) 33e84a324bSAshish Kumar addr = QIXIS_BASE_PHYS; 34e84a324bSAshish Kumar else 35e84a324bSAshish Kumar addr = QIXIS_BASE_PHYS_EARLY; 36e84a324bSAshish Kumar 37e84a324bSAshish Kumar /* 38e84a324bSAshish Kumar * IFC address under 256MB is mapped to 0x30000000, any address above 39e84a324bSAshish Kumar * is mapped to 0x5_10000000 up to 4GB. 40e84a324bSAshish Kumar */ 41e84a324bSAshish Kumar addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; 42e84a324bSAshish Kumar 43e84a324bSAshish Kumar return addr; 44e84a324bSAshish Kumar } 45e84a324bSAshish Kumar 46e84a324bSAshish Kumar int checkboard(void) 47e84a324bSAshish Kumar { 48e84a324bSAshish Kumar char buf[64]; 49e84a324bSAshish Kumar u8 sw; 50e84a324bSAshish Kumar static const char *const freq[] = {"100", "125", "156.25", 51e84a324bSAshish Kumar "100 separate SSCG"}; 52e84a324bSAshish Kumar int clock; 53e84a324bSAshish Kumar 547769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 557769776aSAshish Kumar printf("Board: LS1088A-QDS, "); 567769776aSAshish Kumar #else 57e84a324bSAshish Kumar printf("Board: LS1088A-RDB, "); 587769776aSAshish Kumar #endif 59e84a324bSAshish Kumar 60e84a324bSAshish Kumar sw = QIXIS_READ(arch); 61e84a324bSAshish Kumar printf("Board Arch: V%d, ", sw >> 4); 62e84a324bSAshish Kumar 637769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 647769776aSAshish Kumar printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); 657769776aSAshish Kumar #else 66e84a324bSAshish Kumar printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); 677769776aSAshish Kumar #endif 68e84a324bSAshish Kumar 69e84a324bSAshish Kumar memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); 70e84a324bSAshish Kumar 71e84a324bSAshish Kumar sw = QIXIS_READ(brdcfg[0]); 72e84a324bSAshish Kumar sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 73e84a324bSAshish Kumar 74e84a324bSAshish Kumar #ifdef CONFIG_SD_BOOT 75e84a324bSAshish Kumar puts("SD card\n"); 76e84a324bSAshish Kumar #endif 77e84a324bSAshish Kumar switch (sw) { 787769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 79e84a324bSAshish Kumar case 0: 807769776aSAshish Kumar case 1: 817769776aSAshish Kumar case 2: 827769776aSAshish Kumar case 3: 837769776aSAshish Kumar case 4: 847769776aSAshish Kumar case 5: 857769776aSAshish Kumar case 6: 867769776aSAshish Kumar case 7: 877769776aSAshish Kumar printf("vBank: %d\n", sw); 887769776aSAshish Kumar break; 897769776aSAshish Kumar case 8: 907769776aSAshish Kumar puts("PromJet\n"); 917769776aSAshish Kumar break; 927769776aSAshish Kumar case 15: 937769776aSAshish Kumar puts("IFCCard\n"); 947769776aSAshish Kumar break; 957769776aSAshish Kumar case 14: 967769776aSAshish Kumar #else 977769776aSAshish Kumar case 0: 987769776aSAshish Kumar #endif 99e84a324bSAshish Kumar puts("QSPI:"); 100e84a324bSAshish Kumar sw = QIXIS_READ(brdcfg[0]); 101e84a324bSAshish Kumar sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT; 102e84a324bSAshish Kumar if (sw == 0 || sw == 4) 103e84a324bSAshish Kumar puts("0\n"); 104e84a324bSAshish Kumar else if (sw == 1) 105e84a324bSAshish Kumar puts("1\n"); 106e84a324bSAshish Kumar else 107e84a324bSAshish Kumar puts("EMU\n"); 108e84a324bSAshish Kumar break; 109e84a324bSAshish Kumar 110e84a324bSAshish Kumar default: 111e84a324bSAshish Kumar printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 112e84a324bSAshish Kumar break; 113e84a324bSAshish Kumar } 114e84a324bSAshish Kumar 1157769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 1167769776aSAshish Kumar printf("FPGA: v%d (%s), build %d", 1177769776aSAshish Kumar (int)QIXIS_READ(scver), qixis_read_tag(buf), 1187769776aSAshish Kumar (int)qixis_read_minor()); 1197769776aSAshish Kumar /* the timestamp string contains "\n" at the end */ 1207769776aSAshish Kumar printf(" on %s", qixis_read_time(buf)); 1217769776aSAshish Kumar #else 122e84a324bSAshish Kumar printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); 1237769776aSAshish Kumar #endif 124e84a324bSAshish Kumar 125e84a324bSAshish Kumar /* 126e84a324bSAshish Kumar * Display the actual SERDES reference clocks as configured by the 127e84a324bSAshish Kumar * dip switches on the board. Note that the SWx registers could 128e84a324bSAshish Kumar * technically be set to force the reference clocks to match the 129e84a324bSAshish Kumar * values that the SERDES expects (or vice versa). For now, however, 130e84a324bSAshish Kumar * we just display both values and hope the user notices when they 131e84a324bSAshish Kumar * don't match. 132e84a324bSAshish Kumar */ 133e84a324bSAshish Kumar puts("SERDES1 Reference : "); 134e84a324bSAshish Kumar sw = QIXIS_READ(brdcfg[2]); 135e84a324bSAshish Kumar clock = (sw >> 6) & 3; 136e84a324bSAshish Kumar printf("Clock1 = %sMHz ", freq[clock]); 137e84a324bSAshish Kumar clock = (sw >> 4) & 3; 138e84a324bSAshish Kumar printf("Clock2 = %sMHz", freq[clock]); 139e84a324bSAshish Kumar 140e84a324bSAshish Kumar puts("\nSERDES2 Reference : "); 141e84a324bSAshish Kumar clock = (sw >> 2) & 3; 142e84a324bSAshish Kumar printf("Clock1 = %sMHz ", freq[clock]); 143e84a324bSAshish Kumar clock = (sw >> 0) & 3; 144e84a324bSAshish Kumar printf("Clock2 = %sMHz\n", freq[clock]); 145e84a324bSAshish Kumar 146e84a324bSAshish Kumar return 0; 147e84a324bSAshish Kumar } 148e84a324bSAshish Kumar 149e84a324bSAshish Kumar bool if_board_diff_clk(void) 150e84a324bSAshish Kumar { 1517769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 1527769776aSAshish Kumar u8 diff_conf = QIXIS_READ(brdcfg[11]); 1537769776aSAshish Kumar return diff_conf & 0x40; 1547769776aSAshish Kumar #else 155e84a324bSAshish Kumar u8 diff_conf = QIXIS_READ(dutcfg[11]); 156e84a324bSAshish Kumar return diff_conf & 0x80; 1577769776aSAshish Kumar #endif 158e84a324bSAshish Kumar } 159e84a324bSAshish Kumar 160e84a324bSAshish Kumar unsigned long get_board_sys_clk(void) 161e84a324bSAshish Kumar { 162e84a324bSAshish Kumar u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 163e84a324bSAshish Kumar 164e84a324bSAshish Kumar switch (sysclk_conf & 0x0f) { 165e84a324bSAshish Kumar case QIXIS_SYSCLK_83: 166e84a324bSAshish Kumar return 83333333; 167e84a324bSAshish Kumar case QIXIS_SYSCLK_100: 168e84a324bSAshish Kumar return 100000000; 169e84a324bSAshish Kumar case QIXIS_SYSCLK_125: 170e84a324bSAshish Kumar return 125000000; 171e84a324bSAshish Kumar case QIXIS_SYSCLK_133: 172e84a324bSAshish Kumar return 133333333; 173e84a324bSAshish Kumar case QIXIS_SYSCLK_150: 174e84a324bSAshish Kumar return 150000000; 175e84a324bSAshish Kumar case QIXIS_SYSCLK_160: 176e84a324bSAshish Kumar return 160000000; 177e84a324bSAshish Kumar case QIXIS_SYSCLK_166: 178e84a324bSAshish Kumar return 166666666; 179e84a324bSAshish Kumar } 180e84a324bSAshish Kumar 181e84a324bSAshish Kumar return 66666666; 182e84a324bSAshish Kumar } 183e84a324bSAshish Kumar 184e84a324bSAshish Kumar unsigned long get_board_ddr_clk(void) 185e84a324bSAshish Kumar { 186e84a324bSAshish Kumar u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 187e84a324bSAshish Kumar 188e84a324bSAshish Kumar if (if_board_diff_clk()) 189e84a324bSAshish Kumar return get_board_sys_clk(); 190e84a324bSAshish Kumar switch ((ddrclk_conf & 0x30) >> 4) { 191e84a324bSAshish Kumar case QIXIS_DDRCLK_100: 192e84a324bSAshish Kumar return 100000000; 193e84a324bSAshish Kumar case QIXIS_DDRCLK_125: 194e84a324bSAshish Kumar return 125000000; 195e84a324bSAshish Kumar case QIXIS_DDRCLK_133: 196e84a324bSAshish Kumar return 133333333; 197e84a324bSAshish Kumar } 198e84a324bSAshish Kumar 199e84a324bSAshish Kumar return 66666666; 200e84a324bSAshish Kumar } 201e84a324bSAshish Kumar 202e84a324bSAshish Kumar int select_i2c_ch_pca9547(u8 ch) 203e84a324bSAshish Kumar { 204e84a324bSAshish Kumar int ret; 205e84a324bSAshish Kumar 206e84a324bSAshish Kumar ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 207e84a324bSAshish Kumar if (ret) { 208e84a324bSAshish Kumar puts("PCA: failed to select proper channel\n"); 209e84a324bSAshish Kumar return ret; 210e84a324bSAshish Kumar } 211e84a324bSAshish Kumar 212e84a324bSAshish Kumar return 0; 213e84a324bSAshish Kumar } 214e84a324bSAshish Kumar 215e84a324bSAshish Kumar void board_retimer_init(void) 216e84a324bSAshish Kumar { 217e84a324bSAshish Kumar u8 reg; 218e84a324bSAshish Kumar 219e84a324bSAshish Kumar /* Retimer is connected to I2C1_CH5 */ 220e84a324bSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH5); 221e84a324bSAshish Kumar 222e84a324bSAshish Kumar /* Access to Control/Shared register */ 223e84a324bSAshish Kumar reg = 0x0; 224e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 225e84a324bSAshish Kumar 226e84a324bSAshish Kumar /* Read device revision and ID */ 227e84a324bSAshish Kumar i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); 228e84a324bSAshish Kumar debug("Retimer version id = 0x%x\n", reg); 229e84a324bSAshish Kumar 230e84a324bSAshish Kumar /* Enable Broadcast. All writes target all channel register sets */ 231e84a324bSAshish Kumar reg = 0x0c; 232e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 233e84a324bSAshish Kumar 234e84a324bSAshish Kumar /* Reset Channel Registers */ 235e84a324bSAshish Kumar i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); 236e84a324bSAshish Kumar reg |= 0x4; 237e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); 238e84a324bSAshish Kumar 239e84a324bSAshish Kumar /* Set data rate as 10.3125 Gbps */ 240e84a324bSAshish Kumar reg = 0x90; 241e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); 242e84a324bSAshish Kumar reg = 0xb3; 243e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); 244e84a324bSAshish Kumar reg = 0x90; 245e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); 246e84a324bSAshish Kumar reg = 0xb3; 247e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); 248e84a324bSAshish Kumar reg = 0xcd; 249e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); 250e84a324bSAshish Kumar 251e84a324bSAshish Kumar /* Select VCO Divider to full rate (000) */ 252e84a324bSAshish Kumar i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); 253e84a324bSAshish Kumar reg &= 0x0f; 254e84a324bSAshish Kumar reg |= 0x70; 255e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); 256e84a324bSAshish Kumar 2577769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 2587769776aSAshish Kumar /* Retimer is connected to I2C1_CH5 */ 2597769776aSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH5); 260e84a324bSAshish Kumar 2617769776aSAshish Kumar /* Access to Control/Shared register */ 2627769776aSAshish Kumar reg = 0x0; 2637769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); 2647769776aSAshish Kumar 2657769776aSAshish Kumar /* Read device revision and ID */ 2667769776aSAshish Kumar i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1); 2677769776aSAshish Kumar debug("Retimer version id = 0x%x\n", reg); 2687769776aSAshish Kumar 2697769776aSAshish Kumar /* Enable Broadcast. All writes target all channel register sets */ 2707769776aSAshish Kumar reg = 0x0c; 2717769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); 2727769776aSAshish Kumar 2737769776aSAshish Kumar /* Reset Channel Registers */ 2747769776aSAshish Kumar i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1); 2757769776aSAshish Kumar reg |= 0x4; 2767769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1); 2777769776aSAshish Kumar 2787769776aSAshish Kumar /* Set data rate as 10.3125 Gbps */ 2797769776aSAshish Kumar reg = 0x90; 2807769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1); 2817769776aSAshish Kumar reg = 0xb3; 2827769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1); 2837769776aSAshish Kumar reg = 0x90; 2847769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1); 2857769776aSAshish Kumar reg = 0xb3; 2867769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1); 2877769776aSAshish Kumar reg = 0xcd; 2887769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1); 2897769776aSAshish Kumar 2907769776aSAshish Kumar /* Select VCO Divider to full rate (000) */ 2917769776aSAshish Kumar i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); 2927769776aSAshish Kumar reg &= 0x0f; 2937769776aSAshish Kumar reg |= 0x70; 2947769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); 2957769776aSAshish Kumar #endif 296e84a324bSAshish Kumar /*return the default channel*/ 297e84a324bSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 298e84a324bSAshish Kumar } 299e84a324bSAshish Kumar 300*44cdb5b6SYangbo Lu #ifdef CONFIG_MISC_INIT_R 301*44cdb5b6SYangbo Lu int misc_init_r(void) 302*44cdb5b6SYangbo Lu { 303*44cdb5b6SYangbo Lu #ifdef CONFIG_TARGET_LS1088ARDB 304*44cdb5b6SYangbo Lu u8 brdcfg5; 305*44cdb5b6SYangbo Lu 306*44cdb5b6SYangbo Lu if (hwconfig("esdhc-force-sd")) { 307*44cdb5b6SYangbo Lu brdcfg5 = QIXIS_READ(brdcfg[5]); 308*44cdb5b6SYangbo Lu brdcfg5 &= ~BRDCFG5_SPISDHC_MASK; 309*44cdb5b6SYangbo Lu brdcfg5 |= BRDCFG5_FORCE_SD; 310*44cdb5b6SYangbo Lu QIXIS_WRITE(brdcfg[5], brdcfg5); 311*44cdb5b6SYangbo Lu } 312*44cdb5b6SYangbo Lu #endif 313*44cdb5b6SYangbo Lu return 0; 314*44cdb5b6SYangbo Lu } 315*44cdb5b6SYangbo Lu #endif 316*44cdb5b6SYangbo Lu 317e84a324bSAshish Kumar int board_init(void) 318e84a324bSAshish Kumar { 319e84a324bSAshish Kumar init_final_memctl_regs(); 320e84a324bSAshish Kumar #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) 321e84a324bSAshish Kumar u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; 322e84a324bSAshish Kumar #endif 323e84a324bSAshish Kumar 324e84a324bSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 325e84a324bSAshish Kumar board_retimer_init(); 326e84a324bSAshish Kumar 327e84a324bSAshish Kumar #ifdef CONFIG_ENV_IS_NOWHERE 328e84a324bSAshish Kumar gd->env_addr = (ulong)&default_environment[0]; 329e84a324bSAshish Kumar #endif 330e84a324bSAshish Kumar 331e84a324bSAshish Kumar #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) 332e84a324bSAshish Kumar /* invert AQR105 IRQ pins polarity */ 333e84a324bSAshish Kumar out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK); 334e84a324bSAshish Kumar #endif 335e84a324bSAshish Kumar 33630c41d21SUdit Agarwal #ifdef CONFIG_FSL_CAAM 33730c41d21SUdit Agarwal sec_init(); 33830c41d21SUdit Agarwal #endif 339e84a324bSAshish Kumar #ifdef CONFIG_FSL_LS_PPA 340e84a324bSAshish Kumar ppa_init(); 341e84a324bSAshish Kumar #endif 342e84a324bSAshish Kumar return 0; 343e84a324bSAshish Kumar } 344e84a324bSAshish Kumar 345e84a324bSAshish Kumar int board_early_init_f(void) 346e84a324bSAshish Kumar { 347e84a324bSAshish Kumar fsl_lsch3_early_init_f(); 348e84a324bSAshish Kumar return 0; 349e84a324bSAshish Kumar } 350e84a324bSAshish Kumar 351e84a324bSAshish Kumar void detail_board_ddr_info(void) 352e84a324bSAshish Kumar { 353e84a324bSAshish Kumar puts("\nDDR "); 354e84a324bSAshish Kumar print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); 355e84a324bSAshish Kumar print_ddr_info(0); 356e84a324bSAshish Kumar } 357e84a324bSAshish Kumar 358e84a324bSAshish Kumar #if defined(CONFIG_ARCH_MISC_INIT) 359e84a324bSAshish Kumar int arch_misc_init(void) 360e84a324bSAshish Kumar { 361e84a324bSAshish Kumar return 0; 362e84a324bSAshish Kumar } 363e84a324bSAshish Kumar #endif 364e84a324bSAshish Kumar 365e84a324bSAshish Kumar #ifdef CONFIG_FSL_MC_ENET 366e84a324bSAshish Kumar void fdt_fixup_board_enet(void *fdt) 367e84a324bSAshish Kumar { 368e84a324bSAshish Kumar int offset; 369e84a324bSAshish Kumar 370e84a324bSAshish Kumar offset = fdt_path_offset(fdt, "/fsl-mc"); 371e84a324bSAshish Kumar 372e84a324bSAshish Kumar if (offset < 0) 373e84a324bSAshish Kumar offset = fdt_path_offset(fdt, "/fsl,dprc@0"); 374e84a324bSAshish Kumar 375e84a324bSAshish Kumar if (offset < 0) { 376e84a324bSAshish Kumar printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", 377e84a324bSAshish Kumar __func__, offset); 378e84a324bSAshish Kumar return; 379e84a324bSAshish Kumar } 380e84a324bSAshish Kumar 381e84a324bSAshish Kumar if (get_mc_boot_status() == 0) 382e84a324bSAshish Kumar fdt_status_okay(fdt, offset); 383e84a324bSAshish Kumar else 384e84a324bSAshish Kumar fdt_status_fail(fdt, offset); 385e84a324bSAshish Kumar } 386e84a324bSAshish Kumar #endif 387e84a324bSAshish Kumar 388e84a324bSAshish Kumar #ifdef CONFIG_OF_BOARD_SETUP 3896b6b7e8aSAshish Kumar void fsl_fdt_fixup_flash(void *fdt) 3906b6b7e8aSAshish Kumar { 3916b6b7e8aSAshish Kumar int offset; 3926b6b7e8aSAshish Kumar 3936b6b7e8aSAshish Kumar /* 3946b6b7e8aSAshish Kumar * IFC-NOR and QSPI are muxed on SoC. 3956b6b7e8aSAshish Kumar * So disable IFC node in dts if QSPI is enabled or 3966b6b7e8aSAshish Kumar * disable QSPI node in dts in case QSPI is not enabled. 3976b6b7e8aSAshish Kumar */ 3986b6b7e8aSAshish Kumar 3996b6b7e8aSAshish Kumar #ifdef CONFIG_FSL_QSPI 4006b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/soc/ifc/nor"); 4016b6b7e8aSAshish Kumar 4026b6b7e8aSAshish Kumar if (offset < 0) 4036b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/ifc/nor"); 4046b6b7e8aSAshish Kumar #else 4056b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/soc/quadspi"); 4066b6b7e8aSAshish Kumar 4076b6b7e8aSAshish Kumar if (offset < 0) 4086b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/quadspi"); 4096b6b7e8aSAshish Kumar #endif 4106b6b7e8aSAshish Kumar if (offset < 0) 4116b6b7e8aSAshish Kumar return; 4126b6b7e8aSAshish Kumar 4136b6b7e8aSAshish Kumar fdt_status_disabled(fdt, offset); 4146b6b7e8aSAshish Kumar } 4156b6b7e8aSAshish Kumar 416e84a324bSAshish Kumar int ft_board_setup(void *blob, bd_t *bd) 417e84a324bSAshish Kumar { 418e84a324bSAshish Kumar int err, i; 419e84a324bSAshish Kumar u64 base[CONFIG_NR_DRAM_BANKS]; 420e84a324bSAshish Kumar u64 size[CONFIG_NR_DRAM_BANKS]; 421e84a324bSAshish Kumar 422e84a324bSAshish Kumar ft_cpu_setup(blob, bd); 423e84a324bSAshish Kumar 424e84a324bSAshish Kumar /* fixup DT for the two GPP DDR banks */ 425e84a324bSAshish Kumar for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 426e84a324bSAshish Kumar base[i] = gd->bd->bi_dram[i].start; 427e84a324bSAshish Kumar size[i] = gd->bd->bi_dram[i].size; 428e84a324bSAshish Kumar } 429e84a324bSAshish Kumar 430e84a324bSAshish Kumar #ifdef CONFIG_RESV_RAM 431e84a324bSAshish Kumar /* reduce size if reserved memory is within this bank */ 432e84a324bSAshish Kumar if (gd->arch.resv_ram >= base[0] && 433e84a324bSAshish Kumar gd->arch.resv_ram < base[0] + size[0]) 434e84a324bSAshish Kumar size[0] = gd->arch.resv_ram - base[0]; 435e84a324bSAshish Kumar else if (gd->arch.resv_ram >= base[1] && 436e84a324bSAshish Kumar gd->arch.resv_ram < base[1] + size[1]) 437e84a324bSAshish Kumar size[1] = gd->arch.resv_ram - base[1]; 438e84a324bSAshish Kumar #endif 439e84a324bSAshish Kumar 440e84a324bSAshish Kumar fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); 441e84a324bSAshish Kumar 4426b6b7e8aSAshish Kumar fsl_fdt_fixup_flash(blob); 4436b6b7e8aSAshish Kumar 444e84a324bSAshish Kumar #ifdef CONFIG_FSL_MC_ENET 445e84a324bSAshish Kumar fdt_fixup_board_enet(blob); 446e84a324bSAshish Kumar err = fsl_mc_ldpaa_exit(bd); 447e84a324bSAshish Kumar if (err) 448e84a324bSAshish Kumar return err; 449e84a324bSAshish Kumar #endif 450e84a324bSAshish Kumar 451e84a324bSAshish Kumar return 0; 452e84a324bSAshish Kumar } 453e84a324bSAshish Kumar #endif 454