1e84a324bSAshish Kumar /* 2e84a324bSAshish Kumar * Copyright 2017 NXP 3e84a324bSAshish Kumar * 4e84a324bSAshish Kumar * SPDX-License-Identifier: GPL-2.0+ 5e84a324bSAshish Kumar */ 6e84a324bSAshish Kumar #include <common.h> 7e84a324bSAshish Kumar #include <i2c.h> 8e84a324bSAshish Kumar #include <malloc.h> 9e84a324bSAshish Kumar #include <errno.h> 10e84a324bSAshish Kumar #include <netdev.h> 11e84a324bSAshish Kumar #include <fsl_ifc.h> 12e84a324bSAshish Kumar #include <fsl_ddr.h> 13e84a324bSAshish Kumar #include <fsl_sec.h> 14e84a324bSAshish Kumar #include <asm/io.h> 15e84a324bSAshish Kumar #include <fdt_support.h> 16b08c8c48SMasahiro Yamada #include <linux/libfdt.h> 17e84a324bSAshish Kumar #include <fsl-mc/fsl_mc.h> 18e84a324bSAshish Kumar #include <environment.h> 19e84a324bSAshish Kumar #include <asm/arch-fsl-layerscape/soc.h> 20e84a324bSAshish Kumar #include <asm/arch/ppa.h> 2144cdb5b6SYangbo Lu #include <hwconfig.h> 22ef0789b7SRajesh Bhagat #include <asm/arch/fsl_serdes.h> 23ef0789b7SRajesh Bhagat #include <asm/arch/soc.h> 24e84a324bSAshish Kumar 25e84a324bSAshish Kumar #include "../common/qixis.h" 26e84a324bSAshish Kumar #include "ls1088a_qixis.h" 27ef0789b7SRajesh Bhagat #include "../common/vid.h" 28ef0789b7SRajesh Bhagat #include <fsl_immap.h> 29e84a324bSAshish Kumar 30e84a324bSAshish Kumar DECLARE_GLOBAL_DATA_PTR; 31e84a324bSAshish Kumar 3210e7eaf0SSumit Garg int board_early_init_f(void) 3310e7eaf0SSumit Garg { 34*169d493bSAshish Kumar #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS) 35*169d493bSAshish Kumar i2c_early_init_f(); 36*169d493bSAshish Kumar #endif 3710e7eaf0SSumit Garg fsl_lsch3_early_init_f(); 3810e7eaf0SSumit Garg return 0; 3910e7eaf0SSumit Garg } 4010e7eaf0SSumit Garg 4110e7eaf0SSumit Garg #ifdef CONFIG_FSL_QIXIS 42e84a324bSAshish Kumar unsigned long long get_qixis_addr(void) 43e84a324bSAshish Kumar { 44e84a324bSAshish Kumar unsigned long long addr; 45e84a324bSAshish Kumar 46e84a324bSAshish Kumar if (gd->flags & GD_FLG_RELOC) 47e84a324bSAshish Kumar addr = QIXIS_BASE_PHYS; 48e84a324bSAshish Kumar else 49e84a324bSAshish Kumar addr = QIXIS_BASE_PHYS_EARLY; 50e84a324bSAshish Kumar 51e84a324bSAshish Kumar /* 52e84a324bSAshish Kumar * IFC address under 256MB is mapped to 0x30000000, any address above 53e84a324bSAshish Kumar * is mapped to 0x5_10000000 up to 4GB. 54e84a324bSAshish Kumar */ 55e84a324bSAshish Kumar addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; 56e84a324bSAshish Kumar 57e84a324bSAshish Kumar return addr; 58e84a324bSAshish Kumar } 5910e7eaf0SSumit Garg #endif 60e84a324bSAshish Kumar 61ef0789b7SRajesh Bhagat #if defined(CONFIG_VID) 62ef0789b7SRajesh Bhagat int init_func_vid(void) 63ef0789b7SRajesh Bhagat { 64ef0789b7SRajesh Bhagat if (adjust_vdd(0) < 0) 65ef0789b7SRajesh Bhagat printf("core voltage not adjusted\n"); 66ef0789b7SRajesh Bhagat 67ef0789b7SRajesh Bhagat return 0; 68ef0789b7SRajesh Bhagat } 69ef0789b7SRajesh Bhagat #endif 70ef0789b7SRajesh Bhagat 7110e7eaf0SSumit Garg #if !defined(CONFIG_SPL_BUILD) 72e84a324bSAshish Kumar int checkboard(void) 73e84a324bSAshish Kumar { 74e84a324bSAshish Kumar char buf[64]; 75e84a324bSAshish Kumar u8 sw; 76e84a324bSAshish Kumar static const char *const freq[] = {"100", "125", "156.25", 77e84a324bSAshish Kumar "100 separate SSCG"}; 78e84a324bSAshish Kumar int clock; 79e84a324bSAshish Kumar 807769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 817769776aSAshish Kumar printf("Board: LS1088A-QDS, "); 827769776aSAshish Kumar #else 83e84a324bSAshish Kumar printf("Board: LS1088A-RDB, "); 847769776aSAshish Kumar #endif 85e84a324bSAshish Kumar 86e84a324bSAshish Kumar sw = QIXIS_READ(arch); 87e84a324bSAshish Kumar printf("Board Arch: V%d, ", sw >> 4); 88e84a324bSAshish Kumar 897769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 907769776aSAshish Kumar printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); 917769776aSAshish Kumar #else 92e84a324bSAshish Kumar printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); 937769776aSAshish Kumar #endif 94e84a324bSAshish Kumar 95e84a324bSAshish Kumar memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); 96e84a324bSAshish Kumar 97e84a324bSAshish Kumar sw = QIXIS_READ(brdcfg[0]); 98e84a324bSAshish Kumar sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 99e84a324bSAshish Kumar 100e84a324bSAshish Kumar #ifdef CONFIG_SD_BOOT 101e84a324bSAshish Kumar puts("SD card\n"); 102e84a324bSAshish Kumar #endif 103e84a324bSAshish Kumar switch (sw) { 1047769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 105e84a324bSAshish Kumar case 0: 1067769776aSAshish Kumar case 1: 1077769776aSAshish Kumar case 2: 1087769776aSAshish Kumar case 3: 1097769776aSAshish Kumar case 4: 1107769776aSAshish Kumar case 5: 1117769776aSAshish Kumar case 6: 1127769776aSAshish Kumar case 7: 1137769776aSAshish Kumar printf("vBank: %d\n", sw); 1147769776aSAshish Kumar break; 1157769776aSAshish Kumar case 8: 1167769776aSAshish Kumar puts("PromJet\n"); 1177769776aSAshish Kumar break; 1187769776aSAshish Kumar case 15: 1197769776aSAshish Kumar puts("IFCCard\n"); 1207769776aSAshish Kumar break; 1217769776aSAshish Kumar case 14: 1227769776aSAshish Kumar #else 1237769776aSAshish Kumar case 0: 1247769776aSAshish Kumar #endif 125e84a324bSAshish Kumar puts("QSPI:"); 126e84a324bSAshish Kumar sw = QIXIS_READ(brdcfg[0]); 127e84a324bSAshish Kumar sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT; 128e84a324bSAshish Kumar if (sw == 0 || sw == 4) 129e84a324bSAshish Kumar puts("0\n"); 130e84a324bSAshish Kumar else if (sw == 1) 131e84a324bSAshish Kumar puts("1\n"); 132e84a324bSAshish Kumar else 133e84a324bSAshish Kumar puts("EMU\n"); 134e84a324bSAshish Kumar break; 135e84a324bSAshish Kumar 136e84a324bSAshish Kumar default: 137e84a324bSAshish Kumar printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 138e84a324bSAshish Kumar break; 139e84a324bSAshish Kumar } 140e84a324bSAshish Kumar 1417769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 1427769776aSAshish Kumar printf("FPGA: v%d (%s), build %d", 1437769776aSAshish Kumar (int)QIXIS_READ(scver), qixis_read_tag(buf), 1447769776aSAshish Kumar (int)qixis_read_minor()); 1457769776aSAshish Kumar /* the timestamp string contains "\n" at the end */ 1467769776aSAshish Kumar printf(" on %s", qixis_read_time(buf)); 1477769776aSAshish Kumar #else 148e84a324bSAshish Kumar printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); 1497769776aSAshish Kumar #endif 150e84a324bSAshish Kumar 151e84a324bSAshish Kumar /* 152e84a324bSAshish Kumar * Display the actual SERDES reference clocks as configured by the 153e84a324bSAshish Kumar * dip switches on the board. Note that the SWx registers could 154e84a324bSAshish Kumar * technically be set to force the reference clocks to match the 155e84a324bSAshish Kumar * values that the SERDES expects (or vice versa). For now, however, 156e84a324bSAshish Kumar * we just display both values and hope the user notices when they 157e84a324bSAshish Kumar * don't match. 158e84a324bSAshish Kumar */ 159e84a324bSAshish Kumar puts("SERDES1 Reference : "); 160e84a324bSAshish Kumar sw = QIXIS_READ(brdcfg[2]); 161e84a324bSAshish Kumar clock = (sw >> 6) & 3; 162e84a324bSAshish Kumar printf("Clock1 = %sMHz ", freq[clock]); 163e84a324bSAshish Kumar clock = (sw >> 4) & 3; 164e84a324bSAshish Kumar printf("Clock2 = %sMHz", freq[clock]); 165e84a324bSAshish Kumar 166e84a324bSAshish Kumar puts("\nSERDES2 Reference : "); 167e84a324bSAshish Kumar clock = (sw >> 2) & 3; 168e84a324bSAshish Kumar printf("Clock1 = %sMHz ", freq[clock]); 169e84a324bSAshish Kumar clock = (sw >> 0) & 3; 170e84a324bSAshish Kumar printf("Clock2 = %sMHz\n", freq[clock]); 171e84a324bSAshish Kumar 172e84a324bSAshish Kumar return 0; 173e84a324bSAshish Kumar } 174d12b166aSAshish Kumar #endif 175e84a324bSAshish Kumar 176e84a324bSAshish Kumar bool if_board_diff_clk(void) 177e84a324bSAshish Kumar { 1787769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 1797769776aSAshish Kumar u8 diff_conf = QIXIS_READ(brdcfg[11]); 1807769776aSAshish Kumar return diff_conf & 0x40; 1817769776aSAshish Kumar #else 182e84a324bSAshish Kumar u8 diff_conf = QIXIS_READ(dutcfg[11]); 183e84a324bSAshish Kumar return diff_conf & 0x80; 1847769776aSAshish Kumar #endif 185e84a324bSAshish Kumar } 186e84a324bSAshish Kumar 187e84a324bSAshish Kumar unsigned long get_board_sys_clk(void) 188e84a324bSAshish Kumar { 189e84a324bSAshish Kumar u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 190e84a324bSAshish Kumar 191e84a324bSAshish Kumar switch (sysclk_conf & 0x0f) { 192e84a324bSAshish Kumar case QIXIS_SYSCLK_83: 193e84a324bSAshish Kumar return 83333333; 194e84a324bSAshish Kumar case QIXIS_SYSCLK_100: 195e84a324bSAshish Kumar return 100000000; 196e84a324bSAshish Kumar case QIXIS_SYSCLK_125: 197e84a324bSAshish Kumar return 125000000; 198e84a324bSAshish Kumar case QIXIS_SYSCLK_133: 199e84a324bSAshish Kumar return 133333333; 200e84a324bSAshish Kumar case QIXIS_SYSCLK_150: 201e84a324bSAshish Kumar return 150000000; 202e84a324bSAshish Kumar case QIXIS_SYSCLK_160: 203e84a324bSAshish Kumar return 160000000; 204e84a324bSAshish Kumar case QIXIS_SYSCLK_166: 205e84a324bSAshish Kumar return 166666666; 206e84a324bSAshish Kumar } 207e84a324bSAshish Kumar 208e84a324bSAshish Kumar return 66666666; 209e84a324bSAshish Kumar } 210e84a324bSAshish Kumar 211e84a324bSAshish Kumar unsigned long get_board_ddr_clk(void) 212e84a324bSAshish Kumar { 213e84a324bSAshish Kumar u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 214e84a324bSAshish Kumar 215e84a324bSAshish Kumar if (if_board_diff_clk()) 216e84a324bSAshish Kumar return get_board_sys_clk(); 217e84a324bSAshish Kumar switch ((ddrclk_conf & 0x30) >> 4) { 218e84a324bSAshish Kumar case QIXIS_DDRCLK_100: 219e84a324bSAshish Kumar return 100000000; 220e84a324bSAshish Kumar case QIXIS_DDRCLK_125: 221e84a324bSAshish Kumar return 125000000; 222e84a324bSAshish Kumar case QIXIS_DDRCLK_133: 223e84a324bSAshish Kumar return 133333333; 224e84a324bSAshish Kumar } 225e84a324bSAshish Kumar 226e84a324bSAshish Kumar return 66666666; 227e84a324bSAshish Kumar } 228e84a324bSAshish Kumar 229e84a324bSAshish Kumar int select_i2c_ch_pca9547(u8 ch) 230e84a324bSAshish Kumar { 231e84a324bSAshish Kumar int ret; 232e84a324bSAshish Kumar 233e84a324bSAshish Kumar ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 234e84a324bSAshish Kumar if (ret) { 235e84a324bSAshish Kumar puts("PCA: failed to select proper channel\n"); 236e84a324bSAshish Kumar return ret; 237e84a324bSAshish Kumar } 238e84a324bSAshish Kumar 239e84a324bSAshish Kumar return 0; 240e84a324bSAshish Kumar } 241e84a324bSAshish Kumar 242980d61a2SRajesh Bhagat #if !defined(CONFIG_SPL_BUILD) 243e84a324bSAshish Kumar void board_retimer_init(void) 244e84a324bSAshish Kumar { 245e84a324bSAshish Kumar u8 reg; 246e84a324bSAshish Kumar 247e84a324bSAshish Kumar /* Retimer is connected to I2C1_CH5 */ 248e84a324bSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH5); 249e84a324bSAshish Kumar 250e84a324bSAshish Kumar /* Access to Control/Shared register */ 251e84a324bSAshish Kumar reg = 0x0; 252e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 253e84a324bSAshish Kumar 254e84a324bSAshish Kumar /* Read device revision and ID */ 255e84a324bSAshish Kumar i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); 256e84a324bSAshish Kumar debug("Retimer version id = 0x%x\n", reg); 257e84a324bSAshish Kumar 258e84a324bSAshish Kumar /* Enable Broadcast. All writes target all channel register sets */ 259e84a324bSAshish Kumar reg = 0x0c; 260e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 261e84a324bSAshish Kumar 262e84a324bSAshish Kumar /* Reset Channel Registers */ 263e84a324bSAshish Kumar i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); 264e84a324bSAshish Kumar reg |= 0x4; 265e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); 266e84a324bSAshish Kumar 267e84a324bSAshish Kumar /* Set data rate as 10.3125 Gbps */ 268e84a324bSAshish Kumar reg = 0x90; 269e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); 270e84a324bSAshish Kumar reg = 0xb3; 271e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); 272e84a324bSAshish Kumar reg = 0x90; 273e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); 274e84a324bSAshish Kumar reg = 0xb3; 275e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); 276e84a324bSAshish Kumar reg = 0xcd; 277e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); 278e84a324bSAshish Kumar 279e84a324bSAshish Kumar /* Select VCO Divider to full rate (000) */ 280e84a324bSAshish Kumar i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); 281e84a324bSAshish Kumar reg &= 0x0f; 282e84a324bSAshish Kumar reg |= 0x70; 283e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); 284e84a324bSAshish Kumar 2857769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 2867769776aSAshish Kumar /* Retimer is connected to I2C1_CH5 */ 2877769776aSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH5); 288e84a324bSAshish Kumar 2897769776aSAshish Kumar /* Access to Control/Shared register */ 2907769776aSAshish Kumar reg = 0x0; 2917769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); 2927769776aSAshish Kumar 2937769776aSAshish Kumar /* Read device revision and ID */ 2947769776aSAshish Kumar i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1); 2957769776aSAshish Kumar debug("Retimer version id = 0x%x\n", reg); 2967769776aSAshish Kumar 2977769776aSAshish Kumar /* Enable Broadcast. All writes target all channel register sets */ 2987769776aSAshish Kumar reg = 0x0c; 2997769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); 3007769776aSAshish Kumar 3017769776aSAshish Kumar /* Reset Channel Registers */ 3027769776aSAshish Kumar i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1); 3037769776aSAshish Kumar reg |= 0x4; 3047769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1); 3057769776aSAshish Kumar 3067769776aSAshish Kumar /* Set data rate as 10.3125 Gbps */ 3077769776aSAshish Kumar reg = 0x90; 3087769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1); 3097769776aSAshish Kumar reg = 0xb3; 3107769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1); 3117769776aSAshish Kumar reg = 0x90; 3127769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1); 3137769776aSAshish Kumar reg = 0xb3; 3147769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1); 3157769776aSAshish Kumar reg = 0xcd; 3167769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1); 3177769776aSAshish Kumar 3187769776aSAshish Kumar /* Select VCO Divider to full rate (000) */ 3197769776aSAshish Kumar i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); 3207769776aSAshish Kumar reg &= 0x0f; 3217769776aSAshish Kumar reg |= 0x70; 3227769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); 3237769776aSAshish Kumar #endif 324e84a324bSAshish Kumar /*return the default channel*/ 325e84a324bSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 326e84a324bSAshish Kumar } 327e84a324bSAshish Kumar 32844cdb5b6SYangbo Lu #ifdef CONFIG_MISC_INIT_R 32944cdb5b6SYangbo Lu int misc_init_r(void) 33044cdb5b6SYangbo Lu { 33144cdb5b6SYangbo Lu #ifdef CONFIG_TARGET_LS1088ARDB 33244cdb5b6SYangbo Lu u8 brdcfg5; 33344cdb5b6SYangbo Lu 33444cdb5b6SYangbo Lu if (hwconfig("esdhc-force-sd")) { 33544cdb5b6SYangbo Lu brdcfg5 = QIXIS_READ(brdcfg[5]); 33644cdb5b6SYangbo Lu brdcfg5 &= ~BRDCFG5_SPISDHC_MASK; 33744cdb5b6SYangbo Lu brdcfg5 |= BRDCFG5_FORCE_SD; 33844cdb5b6SYangbo Lu QIXIS_WRITE(brdcfg[5], brdcfg5); 33944cdb5b6SYangbo Lu } 34044cdb5b6SYangbo Lu #endif 34144cdb5b6SYangbo Lu return 0; 34244cdb5b6SYangbo Lu } 34344cdb5b6SYangbo Lu #endif 344980d61a2SRajesh Bhagat #endif 34544cdb5b6SYangbo Lu 346ef0789b7SRajesh Bhagat int i2c_multiplexer_select_vid_channel(u8 channel) 347ef0789b7SRajesh Bhagat { 348ef0789b7SRajesh Bhagat return select_i2c_ch_pca9547(channel); 349ef0789b7SRajesh Bhagat } 350ef0789b7SRajesh Bhagat 351ef0789b7SRajesh Bhagat #ifdef CONFIG_TARGET_LS1088AQDS 352ef0789b7SRajesh Bhagat /* read the current value(SVDD) of the LTM Regulator Voltage */ 353ef0789b7SRajesh Bhagat int get_serdes_volt(void) 354ef0789b7SRajesh Bhagat { 355ef0789b7SRajesh Bhagat int ret, vcode = 0; 356ef0789b7SRajesh Bhagat u8 chan = PWM_CHANNEL0; 357ef0789b7SRajesh Bhagat 358ef0789b7SRajesh Bhagat /* Select the PAGE 0 using PMBus commands PAGE for VDD */ 359ef0789b7SRajesh Bhagat ret = i2c_write(I2C_SVDD_MONITOR_ADDR, 360ef0789b7SRajesh Bhagat PMBUS_CMD_PAGE, 1, &chan, 1); 361ef0789b7SRajesh Bhagat if (ret) { 362ef0789b7SRajesh Bhagat printf("VID: failed to select VDD Page 0\n"); 363ef0789b7SRajesh Bhagat return ret; 364ef0789b7SRajesh Bhagat } 365ef0789b7SRajesh Bhagat 366ef0789b7SRajesh Bhagat /* Read the output voltage using PMBus command READ_VOUT */ 367ef0789b7SRajesh Bhagat ret = i2c_read(I2C_SVDD_MONITOR_ADDR, 368ef0789b7SRajesh Bhagat PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); 369ef0789b7SRajesh Bhagat if (ret) { 370ef0789b7SRajesh Bhagat printf("VID: failed to read the volatge\n"); 371ef0789b7SRajesh Bhagat return ret; 372ef0789b7SRajesh Bhagat } 373ef0789b7SRajesh Bhagat 374ef0789b7SRajesh Bhagat return vcode; 375ef0789b7SRajesh Bhagat } 376ef0789b7SRajesh Bhagat 377ef0789b7SRajesh Bhagat int set_serdes_volt(int svdd) 378ef0789b7SRajesh Bhagat { 379ef0789b7SRajesh Bhagat int ret, vdd_last; 380ef0789b7SRajesh Bhagat u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, 381ef0789b7SRajesh Bhagat svdd & 0xFF, (svdd & 0xFF00) >> 8}; 382ef0789b7SRajesh Bhagat 383ef0789b7SRajesh Bhagat /* Write the desired voltage code to the SVDD regulator */ 384ef0789b7SRajesh Bhagat ret = i2c_write(I2C_SVDD_MONITOR_ADDR, 385ef0789b7SRajesh Bhagat PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); 386ef0789b7SRajesh Bhagat if (ret) { 387ef0789b7SRajesh Bhagat printf("VID: I2C failed to write to the volatge regulator\n"); 388ef0789b7SRajesh Bhagat return -1; 389ef0789b7SRajesh Bhagat } 390ef0789b7SRajesh Bhagat 391ef0789b7SRajesh Bhagat /* Wait for the volatge to get to the desired value */ 392ef0789b7SRajesh Bhagat do { 393ef0789b7SRajesh Bhagat vdd_last = get_serdes_volt(); 394ef0789b7SRajesh Bhagat if (vdd_last < 0) { 395ef0789b7SRajesh Bhagat printf("VID: Couldn't read sensor abort VID adjust\n"); 396ef0789b7SRajesh Bhagat return -1; 397ef0789b7SRajesh Bhagat } 398ef0789b7SRajesh Bhagat } while (vdd_last != svdd); 399ef0789b7SRajesh Bhagat 400ef0789b7SRajesh Bhagat return 1; 401ef0789b7SRajesh Bhagat } 402ef0789b7SRajesh Bhagat #else 403ef0789b7SRajesh Bhagat int get_serdes_volt(void) 404ef0789b7SRajesh Bhagat { 405ef0789b7SRajesh Bhagat return 0; 406ef0789b7SRajesh Bhagat } 407ef0789b7SRajesh Bhagat 408ef0789b7SRajesh Bhagat int set_serdes_volt(int svdd) 409ef0789b7SRajesh Bhagat { 410ef0789b7SRajesh Bhagat int ret; 411ef0789b7SRajesh Bhagat u8 brdcfg4; 412ef0789b7SRajesh Bhagat 413ef0789b7SRajesh Bhagat printf("SVDD changing of RDB\n"); 414ef0789b7SRajesh Bhagat 415ef0789b7SRajesh Bhagat /* Read the BRDCFG54 via CLPD */ 416ef0789b7SRajesh Bhagat ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR, 417ef0789b7SRajesh Bhagat QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); 418ef0789b7SRajesh Bhagat if (ret) { 419ef0789b7SRajesh Bhagat printf("VID: I2C failed to read the CPLD BRDCFG4\n"); 420ef0789b7SRajesh Bhagat return -1; 421ef0789b7SRajesh Bhagat } 422ef0789b7SRajesh Bhagat 423ef0789b7SRajesh Bhagat brdcfg4 = brdcfg4 | 0x08; 424ef0789b7SRajesh Bhagat 425ef0789b7SRajesh Bhagat /* Write to the BRDCFG4 */ 426ef0789b7SRajesh Bhagat ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 427ef0789b7SRajesh Bhagat QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); 428ef0789b7SRajesh Bhagat if (ret) { 429ef0789b7SRajesh Bhagat debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n"); 430ef0789b7SRajesh Bhagat return -1; 431ef0789b7SRajesh Bhagat } 432ef0789b7SRajesh Bhagat 433ef0789b7SRajesh Bhagat /* Wait for the volatge to get to the desired value */ 434ef0789b7SRajesh Bhagat udelay(10000); 435ef0789b7SRajesh Bhagat 436ef0789b7SRajesh Bhagat return 1; 437ef0789b7SRajesh Bhagat } 438ef0789b7SRajesh Bhagat #endif 439ef0789b7SRajesh Bhagat 440ef0789b7SRajesh Bhagat /* this function disables the SERDES, changes the SVDD Voltage and enables it*/ 441ef0789b7SRajesh Bhagat int board_adjust_vdd(int vdd) 442ef0789b7SRajesh Bhagat { 443ef0789b7SRajesh Bhagat int ret = 0; 444ef0789b7SRajesh Bhagat 445ef0789b7SRajesh Bhagat debug("%s: vdd = %d\n", __func__, vdd); 446ef0789b7SRajesh Bhagat 447ef0789b7SRajesh Bhagat /* Special settings to be performed when voltage is 900mV */ 448ef0789b7SRajesh Bhagat if (vdd == 900) { 449ef0789b7SRajesh Bhagat ret = setup_serdes_volt(vdd); 450ef0789b7SRajesh Bhagat if (ret < 0) { 451ef0789b7SRajesh Bhagat ret = -1; 452ef0789b7SRajesh Bhagat goto exit; 453ef0789b7SRajesh Bhagat } 454ef0789b7SRajesh Bhagat } 455ef0789b7SRajesh Bhagat exit: 456ef0789b7SRajesh Bhagat return ret; 457ef0789b7SRajesh Bhagat } 458ef0789b7SRajesh Bhagat 459980d61a2SRajesh Bhagat #if !defined(CONFIG_SPL_BUILD) 460e84a324bSAshish Kumar int board_init(void) 461e84a324bSAshish Kumar { 462e84a324bSAshish Kumar init_final_memctl_regs(); 463e84a324bSAshish Kumar #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) 464e84a324bSAshish Kumar u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; 465e84a324bSAshish Kumar #endif 466e84a324bSAshish Kumar 467e84a324bSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 468e84a324bSAshish Kumar board_retimer_init(); 469e84a324bSAshish Kumar 470e84a324bSAshish Kumar #ifdef CONFIG_ENV_IS_NOWHERE 471e84a324bSAshish Kumar gd->env_addr = (ulong)&default_environment[0]; 472e84a324bSAshish Kumar #endif 473e84a324bSAshish Kumar 474e84a324bSAshish Kumar #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) 475e84a324bSAshish Kumar /* invert AQR105 IRQ pins polarity */ 476e84a324bSAshish Kumar out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK); 477e84a324bSAshish Kumar #endif 478e84a324bSAshish Kumar 47930c41d21SUdit Agarwal #ifdef CONFIG_FSL_CAAM 48030c41d21SUdit Agarwal sec_init(); 48130c41d21SUdit Agarwal #endif 482e84a324bSAshish Kumar #ifdef CONFIG_FSL_LS_PPA 483e84a324bSAshish Kumar ppa_init(); 484e84a324bSAshish Kumar #endif 485e84a324bSAshish Kumar return 0; 486e84a324bSAshish Kumar } 487e84a324bSAshish Kumar 488e84a324bSAshish Kumar void detail_board_ddr_info(void) 489e84a324bSAshish Kumar { 490e84a324bSAshish Kumar puts("\nDDR "); 491e84a324bSAshish Kumar print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); 492e84a324bSAshish Kumar print_ddr_info(0); 493e84a324bSAshish Kumar } 494e84a324bSAshish Kumar 495e84a324bSAshish Kumar #if defined(CONFIG_ARCH_MISC_INIT) 496e84a324bSAshish Kumar int arch_misc_init(void) 497e84a324bSAshish Kumar { 498e84a324bSAshish Kumar return 0; 499e84a324bSAshish Kumar } 500e84a324bSAshish Kumar #endif 501e84a324bSAshish Kumar 502e84a324bSAshish Kumar #ifdef CONFIG_FSL_MC_ENET 503e84a324bSAshish Kumar void fdt_fixup_board_enet(void *fdt) 504e84a324bSAshish Kumar { 505e84a324bSAshish Kumar int offset; 506e84a324bSAshish Kumar 507e84a324bSAshish Kumar offset = fdt_path_offset(fdt, "/fsl-mc"); 508e84a324bSAshish Kumar 509e84a324bSAshish Kumar if (offset < 0) 510e84a324bSAshish Kumar offset = fdt_path_offset(fdt, "/fsl,dprc@0"); 511e84a324bSAshish Kumar 512e84a324bSAshish Kumar if (offset < 0) { 513e84a324bSAshish Kumar printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", 514e84a324bSAshish Kumar __func__, offset); 515e84a324bSAshish Kumar return; 516e84a324bSAshish Kumar } 517e84a324bSAshish Kumar 51870a131ebSYogesh Gaur if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) 519e84a324bSAshish Kumar fdt_status_okay(fdt, offset); 520e84a324bSAshish Kumar else 521e84a324bSAshish Kumar fdt_status_fail(fdt, offset); 522e84a324bSAshish Kumar } 523e84a324bSAshish Kumar #endif 524e84a324bSAshish Kumar 525e84a324bSAshish Kumar #ifdef CONFIG_OF_BOARD_SETUP 5266b6b7e8aSAshish Kumar void fsl_fdt_fixup_flash(void *fdt) 5276b6b7e8aSAshish Kumar { 5286b6b7e8aSAshish Kumar int offset; 5296b6b7e8aSAshish Kumar 5306b6b7e8aSAshish Kumar /* 5316b6b7e8aSAshish Kumar * IFC-NOR and QSPI are muxed on SoC. 5326b6b7e8aSAshish Kumar * So disable IFC node in dts if QSPI is enabled or 5336b6b7e8aSAshish Kumar * disable QSPI node in dts in case QSPI is not enabled. 5346b6b7e8aSAshish Kumar */ 5356b6b7e8aSAshish Kumar 5366b6b7e8aSAshish Kumar #ifdef CONFIG_FSL_QSPI 5376b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/soc/ifc/nor"); 5386b6b7e8aSAshish Kumar 5396b6b7e8aSAshish Kumar if (offset < 0) 5406b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/ifc/nor"); 5416b6b7e8aSAshish Kumar #else 5426b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/soc/quadspi"); 5436b6b7e8aSAshish Kumar 5446b6b7e8aSAshish Kumar if (offset < 0) 5456b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/quadspi"); 5466b6b7e8aSAshish Kumar #endif 5476b6b7e8aSAshish Kumar if (offset < 0) 5486b6b7e8aSAshish Kumar return; 5496b6b7e8aSAshish Kumar 5506b6b7e8aSAshish Kumar fdt_status_disabled(fdt, offset); 5516b6b7e8aSAshish Kumar } 5526b6b7e8aSAshish Kumar 553e84a324bSAshish Kumar int ft_board_setup(void *blob, bd_t *bd) 554e84a324bSAshish Kumar { 555e84a324bSAshish Kumar int err, i; 556e84a324bSAshish Kumar u64 base[CONFIG_NR_DRAM_BANKS]; 557e84a324bSAshish Kumar u64 size[CONFIG_NR_DRAM_BANKS]; 558e84a324bSAshish Kumar 559e84a324bSAshish Kumar ft_cpu_setup(blob, bd); 560e84a324bSAshish Kumar 561e84a324bSAshish Kumar /* fixup DT for the two GPP DDR banks */ 562e84a324bSAshish Kumar for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 563e84a324bSAshish Kumar base[i] = gd->bd->bi_dram[i].start; 564e84a324bSAshish Kumar size[i] = gd->bd->bi_dram[i].size; 565e84a324bSAshish Kumar } 566e84a324bSAshish Kumar 567e84a324bSAshish Kumar #ifdef CONFIG_RESV_RAM 568e84a324bSAshish Kumar /* reduce size if reserved memory is within this bank */ 569e84a324bSAshish Kumar if (gd->arch.resv_ram >= base[0] && 570e84a324bSAshish Kumar gd->arch.resv_ram < base[0] + size[0]) 571e84a324bSAshish Kumar size[0] = gd->arch.resv_ram - base[0]; 572e84a324bSAshish Kumar else if (gd->arch.resv_ram >= base[1] && 573e84a324bSAshish Kumar gd->arch.resv_ram < base[1] + size[1]) 574e84a324bSAshish Kumar size[1] = gd->arch.resv_ram - base[1]; 575e84a324bSAshish Kumar #endif 576e84a324bSAshish Kumar 577e84a324bSAshish Kumar fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); 578e84a324bSAshish Kumar 5796b6b7e8aSAshish Kumar fsl_fdt_fixup_flash(blob); 5806b6b7e8aSAshish Kumar 581e84a324bSAshish Kumar #ifdef CONFIG_FSL_MC_ENET 582e84a324bSAshish Kumar fdt_fixup_board_enet(blob); 583e84a324bSAshish Kumar err = fsl_mc_ldpaa_exit(bd); 584e84a324bSAshish Kumar if (err) 585e84a324bSAshish Kumar return err; 586e84a324bSAshish Kumar #endif 587e84a324bSAshish Kumar 588e84a324bSAshish Kumar return 0; 589e84a324bSAshish Kumar } 590e84a324bSAshish Kumar #endif 59110e7eaf0SSumit Garg #endif /* defined(CONFIG_SPL_BUILD) */ 592