1e84a324bSAshish Kumar /* 2e84a324bSAshish Kumar * Copyright 2017 NXP 3e84a324bSAshish Kumar * 4e84a324bSAshish Kumar * SPDX-License-Identifier: GPL-2.0+ 5e84a324bSAshish Kumar */ 6e84a324bSAshish Kumar #include <common.h> 7e84a324bSAshish Kumar #include <i2c.h> 8e84a324bSAshish Kumar #include <malloc.h> 9e84a324bSAshish Kumar #include <errno.h> 10e84a324bSAshish Kumar #include <netdev.h> 11e84a324bSAshish Kumar #include <fsl_ifc.h> 12e84a324bSAshish Kumar #include <fsl_ddr.h> 13e84a324bSAshish Kumar #include <fsl_sec.h> 14e84a324bSAshish Kumar #include <asm/io.h> 15e84a324bSAshish Kumar #include <fdt_support.h> 16e84a324bSAshish Kumar #include <libfdt.h> 17e84a324bSAshish Kumar #include <fsl-mc/fsl_mc.h> 18e84a324bSAshish Kumar #include <environment.h> 19e84a324bSAshish Kumar #include <asm/arch-fsl-layerscape/soc.h> 20e84a324bSAshish Kumar #include <asm/arch/ppa.h> 2144cdb5b6SYangbo Lu #include <hwconfig.h> 22e84a324bSAshish Kumar 23e84a324bSAshish Kumar #include "../common/qixis.h" 24e84a324bSAshish Kumar #include "ls1088a_qixis.h" 25e84a324bSAshish Kumar 26e84a324bSAshish Kumar DECLARE_GLOBAL_DATA_PTR; 27e84a324bSAshish Kumar 28*10e7eaf0SSumit Garg int board_early_init_f(void) 29*10e7eaf0SSumit Garg { 30*10e7eaf0SSumit Garg fsl_lsch3_early_init_f(); 31*10e7eaf0SSumit Garg return 0; 32*10e7eaf0SSumit Garg } 33*10e7eaf0SSumit Garg 34*10e7eaf0SSumit Garg #ifdef CONFIG_FSL_QIXIS 35e84a324bSAshish Kumar unsigned long long get_qixis_addr(void) 36e84a324bSAshish Kumar { 37e84a324bSAshish Kumar unsigned long long addr; 38e84a324bSAshish Kumar 39e84a324bSAshish Kumar if (gd->flags & GD_FLG_RELOC) 40e84a324bSAshish Kumar addr = QIXIS_BASE_PHYS; 41e84a324bSAshish Kumar else 42e84a324bSAshish Kumar addr = QIXIS_BASE_PHYS_EARLY; 43e84a324bSAshish Kumar 44e84a324bSAshish Kumar /* 45e84a324bSAshish Kumar * IFC address under 256MB is mapped to 0x30000000, any address above 46e84a324bSAshish Kumar * is mapped to 0x5_10000000 up to 4GB. 47e84a324bSAshish Kumar */ 48e84a324bSAshish Kumar addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; 49e84a324bSAshish Kumar 50e84a324bSAshish Kumar return addr; 51e84a324bSAshish Kumar } 52*10e7eaf0SSumit Garg #endif 53e84a324bSAshish Kumar 54*10e7eaf0SSumit Garg #if !defined(CONFIG_SPL_BUILD) 55e84a324bSAshish Kumar int checkboard(void) 56e84a324bSAshish Kumar { 57e84a324bSAshish Kumar char buf[64]; 58e84a324bSAshish Kumar u8 sw; 59e84a324bSAshish Kumar static const char *const freq[] = {"100", "125", "156.25", 60e84a324bSAshish Kumar "100 separate SSCG"}; 61e84a324bSAshish Kumar int clock; 62e84a324bSAshish Kumar 637769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 647769776aSAshish Kumar printf("Board: LS1088A-QDS, "); 657769776aSAshish Kumar #else 66e84a324bSAshish Kumar printf("Board: LS1088A-RDB, "); 677769776aSAshish Kumar #endif 68e84a324bSAshish Kumar 69e84a324bSAshish Kumar sw = QIXIS_READ(arch); 70e84a324bSAshish Kumar printf("Board Arch: V%d, ", sw >> 4); 71e84a324bSAshish Kumar 727769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 737769776aSAshish Kumar printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); 747769776aSAshish Kumar #else 75e84a324bSAshish Kumar printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); 767769776aSAshish Kumar #endif 77e84a324bSAshish Kumar 78e84a324bSAshish Kumar memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); 79e84a324bSAshish Kumar 80e84a324bSAshish Kumar sw = QIXIS_READ(brdcfg[0]); 81e84a324bSAshish Kumar sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 82e84a324bSAshish Kumar 83e84a324bSAshish Kumar #ifdef CONFIG_SD_BOOT 84e84a324bSAshish Kumar puts("SD card\n"); 85e84a324bSAshish Kumar #endif 86e84a324bSAshish Kumar switch (sw) { 877769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 88e84a324bSAshish Kumar case 0: 897769776aSAshish Kumar case 1: 907769776aSAshish Kumar case 2: 917769776aSAshish Kumar case 3: 927769776aSAshish Kumar case 4: 937769776aSAshish Kumar case 5: 947769776aSAshish Kumar case 6: 957769776aSAshish Kumar case 7: 967769776aSAshish Kumar printf("vBank: %d\n", sw); 977769776aSAshish Kumar break; 987769776aSAshish Kumar case 8: 997769776aSAshish Kumar puts("PromJet\n"); 1007769776aSAshish Kumar break; 1017769776aSAshish Kumar case 15: 1027769776aSAshish Kumar puts("IFCCard\n"); 1037769776aSAshish Kumar break; 1047769776aSAshish Kumar case 14: 1057769776aSAshish Kumar #else 1067769776aSAshish Kumar case 0: 1077769776aSAshish Kumar #endif 108e84a324bSAshish Kumar puts("QSPI:"); 109e84a324bSAshish Kumar sw = QIXIS_READ(brdcfg[0]); 110e84a324bSAshish Kumar sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT; 111e84a324bSAshish Kumar if (sw == 0 || sw == 4) 112e84a324bSAshish Kumar puts("0\n"); 113e84a324bSAshish Kumar else if (sw == 1) 114e84a324bSAshish Kumar puts("1\n"); 115e84a324bSAshish Kumar else 116e84a324bSAshish Kumar puts("EMU\n"); 117e84a324bSAshish Kumar break; 118e84a324bSAshish Kumar 119e84a324bSAshish Kumar default: 120e84a324bSAshish Kumar printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 121e84a324bSAshish Kumar break; 122e84a324bSAshish Kumar } 123e84a324bSAshish Kumar 1247769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 1257769776aSAshish Kumar printf("FPGA: v%d (%s), build %d", 1267769776aSAshish Kumar (int)QIXIS_READ(scver), qixis_read_tag(buf), 1277769776aSAshish Kumar (int)qixis_read_minor()); 1287769776aSAshish Kumar /* the timestamp string contains "\n" at the end */ 1297769776aSAshish Kumar printf(" on %s", qixis_read_time(buf)); 1307769776aSAshish Kumar #else 131e84a324bSAshish Kumar printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); 1327769776aSAshish Kumar #endif 133e84a324bSAshish Kumar 134e84a324bSAshish Kumar /* 135e84a324bSAshish Kumar * Display the actual SERDES reference clocks as configured by the 136e84a324bSAshish Kumar * dip switches on the board. Note that the SWx registers could 137e84a324bSAshish Kumar * technically be set to force the reference clocks to match the 138e84a324bSAshish Kumar * values that the SERDES expects (or vice versa). For now, however, 139e84a324bSAshish Kumar * we just display both values and hope the user notices when they 140e84a324bSAshish Kumar * don't match. 141e84a324bSAshish Kumar */ 142e84a324bSAshish Kumar puts("SERDES1 Reference : "); 143e84a324bSAshish Kumar sw = QIXIS_READ(brdcfg[2]); 144e84a324bSAshish Kumar clock = (sw >> 6) & 3; 145e84a324bSAshish Kumar printf("Clock1 = %sMHz ", freq[clock]); 146e84a324bSAshish Kumar clock = (sw >> 4) & 3; 147e84a324bSAshish Kumar printf("Clock2 = %sMHz", freq[clock]); 148e84a324bSAshish Kumar 149e84a324bSAshish Kumar puts("\nSERDES2 Reference : "); 150e84a324bSAshish Kumar clock = (sw >> 2) & 3; 151e84a324bSAshish Kumar printf("Clock1 = %sMHz ", freq[clock]); 152e84a324bSAshish Kumar clock = (sw >> 0) & 3; 153e84a324bSAshish Kumar printf("Clock2 = %sMHz\n", freq[clock]); 154e84a324bSAshish Kumar 155e84a324bSAshish Kumar return 0; 156e84a324bSAshish Kumar } 157e84a324bSAshish Kumar 158e84a324bSAshish Kumar bool if_board_diff_clk(void) 159e84a324bSAshish Kumar { 1607769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 1617769776aSAshish Kumar u8 diff_conf = QIXIS_READ(brdcfg[11]); 1627769776aSAshish Kumar return diff_conf & 0x40; 1637769776aSAshish Kumar #else 164e84a324bSAshish Kumar u8 diff_conf = QIXIS_READ(dutcfg[11]); 165e84a324bSAshish Kumar return diff_conf & 0x80; 1667769776aSAshish Kumar #endif 167e84a324bSAshish Kumar } 168e84a324bSAshish Kumar 169e84a324bSAshish Kumar unsigned long get_board_sys_clk(void) 170e84a324bSAshish Kumar { 171e84a324bSAshish Kumar u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 172e84a324bSAshish Kumar 173e84a324bSAshish Kumar switch (sysclk_conf & 0x0f) { 174e84a324bSAshish Kumar case QIXIS_SYSCLK_83: 175e84a324bSAshish Kumar return 83333333; 176e84a324bSAshish Kumar case QIXIS_SYSCLK_100: 177e84a324bSAshish Kumar return 100000000; 178e84a324bSAshish Kumar case QIXIS_SYSCLK_125: 179e84a324bSAshish Kumar return 125000000; 180e84a324bSAshish Kumar case QIXIS_SYSCLK_133: 181e84a324bSAshish Kumar return 133333333; 182e84a324bSAshish Kumar case QIXIS_SYSCLK_150: 183e84a324bSAshish Kumar return 150000000; 184e84a324bSAshish Kumar case QIXIS_SYSCLK_160: 185e84a324bSAshish Kumar return 160000000; 186e84a324bSAshish Kumar case QIXIS_SYSCLK_166: 187e84a324bSAshish Kumar return 166666666; 188e84a324bSAshish Kumar } 189e84a324bSAshish Kumar 190e84a324bSAshish Kumar return 66666666; 191e84a324bSAshish Kumar } 192e84a324bSAshish Kumar 193e84a324bSAshish Kumar unsigned long get_board_ddr_clk(void) 194e84a324bSAshish Kumar { 195e84a324bSAshish Kumar u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 196e84a324bSAshish Kumar 197e84a324bSAshish Kumar if (if_board_diff_clk()) 198e84a324bSAshish Kumar return get_board_sys_clk(); 199e84a324bSAshish Kumar switch ((ddrclk_conf & 0x30) >> 4) { 200e84a324bSAshish Kumar case QIXIS_DDRCLK_100: 201e84a324bSAshish Kumar return 100000000; 202e84a324bSAshish Kumar case QIXIS_DDRCLK_125: 203e84a324bSAshish Kumar return 125000000; 204e84a324bSAshish Kumar case QIXIS_DDRCLK_133: 205e84a324bSAshish Kumar return 133333333; 206e84a324bSAshish Kumar } 207e84a324bSAshish Kumar 208e84a324bSAshish Kumar return 66666666; 209e84a324bSAshish Kumar } 210e84a324bSAshish Kumar 211e84a324bSAshish Kumar int select_i2c_ch_pca9547(u8 ch) 212e84a324bSAshish Kumar { 213e84a324bSAshish Kumar int ret; 214e84a324bSAshish Kumar 215e84a324bSAshish Kumar ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 216e84a324bSAshish Kumar if (ret) { 217e84a324bSAshish Kumar puts("PCA: failed to select proper channel\n"); 218e84a324bSAshish Kumar return ret; 219e84a324bSAshish Kumar } 220e84a324bSAshish Kumar 221e84a324bSAshish Kumar return 0; 222e84a324bSAshish Kumar } 223e84a324bSAshish Kumar 224e84a324bSAshish Kumar void board_retimer_init(void) 225e84a324bSAshish Kumar { 226e84a324bSAshish Kumar u8 reg; 227e84a324bSAshish Kumar 228e84a324bSAshish Kumar /* Retimer is connected to I2C1_CH5 */ 229e84a324bSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH5); 230e84a324bSAshish Kumar 231e84a324bSAshish Kumar /* Access to Control/Shared register */ 232e84a324bSAshish Kumar reg = 0x0; 233e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 234e84a324bSAshish Kumar 235e84a324bSAshish Kumar /* Read device revision and ID */ 236e84a324bSAshish Kumar i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); 237e84a324bSAshish Kumar debug("Retimer version id = 0x%x\n", reg); 238e84a324bSAshish Kumar 239e84a324bSAshish Kumar /* Enable Broadcast. All writes target all channel register sets */ 240e84a324bSAshish Kumar reg = 0x0c; 241e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 242e84a324bSAshish Kumar 243e84a324bSAshish Kumar /* Reset Channel Registers */ 244e84a324bSAshish Kumar i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); 245e84a324bSAshish Kumar reg |= 0x4; 246e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); 247e84a324bSAshish Kumar 248e84a324bSAshish Kumar /* Set data rate as 10.3125 Gbps */ 249e84a324bSAshish Kumar reg = 0x90; 250e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); 251e84a324bSAshish Kumar reg = 0xb3; 252e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); 253e84a324bSAshish Kumar reg = 0x90; 254e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); 255e84a324bSAshish Kumar reg = 0xb3; 256e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); 257e84a324bSAshish Kumar reg = 0xcd; 258e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); 259e84a324bSAshish Kumar 260e84a324bSAshish Kumar /* Select VCO Divider to full rate (000) */ 261e84a324bSAshish Kumar i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); 262e84a324bSAshish Kumar reg &= 0x0f; 263e84a324bSAshish Kumar reg |= 0x70; 264e84a324bSAshish Kumar i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); 265e84a324bSAshish Kumar 2667769776aSAshish Kumar #ifdef CONFIG_TARGET_LS1088AQDS 2677769776aSAshish Kumar /* Retimer is connected to I2C1_CH5 */ 2687769776aSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH5); 269e84a324bSAshish Kumar 2707769776aSAshish Kumar /* Access to Control/Shared register */ 2717769776aSAshish Kumar reg = 0x0; 2727769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); 2737769776aSAshish Kumar 2747769776aSAshish Kumar /* Read device revision and ID */ 2757769776aSAshish Kumar i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1); 2767769776aSAshish Kumar debug("Retimer version id = 0x%x\n", reg); 2777769776aSAshish Kumar 2787769776aSAshish Kumar /* Enable Broadcast. All writes target all channel register sets */ 2797769776aSAshish Kumar reg = 0x0c; 2807769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); 2817769776aSAshish Kumar 2827769776aSAshish Kumar /* Reset Channel Registers */ 2837769776aSAshish Kumar i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1); 2847769776aSAshish Kumar reg |= 0x4; 2857769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1); 2867769776aSAshish Kumar 2877769776aSAshish Kumar /* Set data rate as 10.3125 Gbps */ 2887769776aSAshish Kumar reg = 0x90; 2897769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1); 2907769776aSAshish Kumar reg = 0xb3; 2917769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1); 2927769776aSAshish Kumar reg = 0x90; 2937769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1); 2947769776aSAshish Kumar reg = 0xb3; 2957769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1); 2967769776aSAshish Kumar reg = 0xcd; 2977769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1); 2987769776aSAshish Kumar 2997769776aSAshish Kumar /* Select VCO Divider to full rate (000) */ 3007769776aSAshish Kumar i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); 3017769776aSAshish Kumar reg &= 0x0f; 3027769776aSAshish Kumar reg |= 0x70; 3037769776aSAshish Kumar i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); 3047769776aSAshish Kumar #endif 305e84a324bSAshish Kumar /*return the default channel*/ 306e84a324bSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 307e84a324bSAshish Kumar } 308e84a324bSAshish Kumar 30944cdb5b6SYangbo Lu #ifdef CONFIG_MISC_INIT_R 31044cdb5b6SYangbo Lu int misc_init_r(void) 31144cdb5b6SYangbo Lu { 31244cdb5b6SYangbo Lu #ifdef CONFIG_TARGET_LS1088ARDB 31344cdb5b6SYangbo Lu u8 brdcfg5; 31444cdb5b6SYangbo Lu 31544cdb5b6SYangbo Lu if (hwconfig("esdhc-force-sd")) { 31644cdb5b6SYangbo Lu brdcfg5 = QIXIS_READ(brdcfg[5]); 31744cdb5b6SYangbo Lu brdcfg5 &= ~BRDCFG5_SPISDHC_MASK; 31844cdb5b6SYangbo Lu brdcfg5 |= BRDCFG5_FORCE_SD; 31944cdb5b6SYangbo Lu QIXIS_WRITE(brdcfg[5], brdcfg5); 32044cdb5b6SYangbo Lu } 32144cdb5b6SYangbo Lu #endif 32244cdb5b6SYangbo Lu return 0; 32344cdb5b6SYangbo Lu } 32444cdb5b6SYangbo Lu #endif 32544cdb5b6SYangbo Lu 326e84a324bSAshish Kumar int board_init(void) 327e84a324bSAshish Kumar { 328e84a324bSAshish Kumar init_final_memctl_regs(); 329e84a324bSAshish Kumar #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) 330e84a324bSAshish Kumar u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; 331e84a324bSAshish Kumar #endif 332e84a324bSAshish Kumar 333e84a324bSAshish Kumar select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 334e84a324bSAshish Kumar board_retimer_init(); 335e84a324bSAshish Kumar 336e84a324bSAshish Kumar #ifdef CONFIG_ENV_IS_NOWHERE 337e84a324bSAshish Kumar gd->env_addr = (ulong)&default_environment[0]; 338e84a324bSAshish Kumar #endif 339e84a324bSAshish Kumar 340e84a324bSAshish Kumar #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) 341e84a324bSAshish Kumar /* invert AQR105 IRQ pins polarity */ 342e84a324bSAshish Kumar out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK); 343e84a324bSAshish Kumar #endif 344e84a324bSAshish Kumar 34530c41d21SUdit Agarwal #ifdef CONFIG_FSL_CAAM 34630c41d21SUdit Agarwal sec_init(); 34730c41d21SUdit Agarwal #endif 348e84a324bSAshish Kumar #ifdef CONFIG_FSL_LS_PPA 349e84a324bSAshish Kumar ppa_init(); 350e84a324bSAshish Kumar #endif 351e84a324bSAshish Kumar return 0; 352e84a324bSAshish Kumar } 353e84a324bSAshish Kumar 354e84a324bSAshish Kumar void detail_board_ddr_info(void) 355e84a324bSAshish Kumar { 356e84a324bSAshish Kumar puts("\nDDR "); 357e84a324bSAshish Kumar print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); 358e84a324bSAshish Kumar print_ddr_info(0); 359e84a324bSAshish Kumar } 360e84a324bSAshish Kumar 361e84a324bSAshish Kumar #if defined(CONFIG_ARCH_MISC_INIT) 362e84a324bSAshish Kumar int arch_misc_init(void) 363e84a324bSAshish Kumar { 364e84a324bSAshish Kumar return 0; 365e84a324bSAshish Kumar } 366e84a324bSAshish Kumar #endif 367e84a324bSAshish Kumar 368e84a324bSAshish Kumar #ifdef CONFIG_FSL_MC_ENET 369e84a324bSAshish Kumar void fdt_fixup_board_enet(void *fdt) 370e84a324bSAshish Kumar { 371e84a324bSAshish Kumar int offset; 372e84a324bSAshish Kumar 373e84a324bSAshish Kumar offset = fdt_path_offset(fdt, "/fsl-mc"); 374e84a324bSAshish Kumar 375e84a324bSAshish Kumar if (offset < 0) 376e84a324bSAshish Kumar offset = fdt_path_offset(fdt, "/fsl,dprc@0"); 377e84a324bSAshish Kumar 378e84a324bSAshish Kumar if (offset < 0) { 379e84a324bSAshish Kumar printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", 380e84a324bSAshish Kumar __func__, offset); 381e84a324bSAshish Kumar return; 382e84a324bSAshish Kumar } 383e84a324bSAshish Kumar 38470a131ebSYogesh Gaur if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) 385e84a324bSAshish Kumar fdt_status_okay(fdt, offset); 386e84a324bSAshish Kumar else 387e84a324bSAshish Kumar fdt_status_fail(fdt, offset); 388e84a324bSAshish Kumar } 389e84a324bSAshish Kumar #endif 390e84a324bSAshish Kumar 391e84a324bSAshish Kumar #ifdef CONFIG_OF_BOARD_SETUP 3926b6b7e8aSAshish Kumar void fsl_fdt_fixup_flash(void *fdt) 3936b6b7e8aSAshish Kumar { 3946b6b7e8aSAshish Kumar int offset; 3956b6b7e8aSAshish Kumar 3966b6b7e8aSAshish Kumar /* 3976b6b7e8aSAshish Kumar * IFC-NOR and QSPI are muxed on SoC. 3986b6b7e8aSAshish Kumar * So disable IFC node in dts if QSPI is enabled or 3996b6b7e8aSAshish Kumar * disable QSPI node in dts in case QSPI is not enabled. 4006b6b7e8aSAshish Kumar */ 4016b6b7e8aSAshish Kumar 4026b6b7e8aSAshish Kumar #ifdef CONFIG_FSL_QSPI 4036b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/soc/ifc/nor"); 4046b6b7e8aSAshish Kumar 4056b6b7e8aSAshish Kumar if (offset < 0) 4066b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/ifc/nor"); 4076b6b7e8aSAshish Kumar #else 4086b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/soc/quadspi"); 4096b6b7e8aSAshish Kumar 4106b6b7e8aSAshish Kumar if (offset < 0) 4116b6b7e8aSAshish Kumar offset = fdt_path_offset(fdt, "/quadspi"); 4126b6b7e8aSAshish Kumar #endif 4136b6b7e8aSAshish Kumar if (offset < 0) 4146b6b7e8aSAshish Kumar return; 4156b6b7e8aSAshish Kumar 4166b6b7e8aSAshish Kumar fdt_status_disabled(fdt, offset); 4176b6b7e8aSAshish Kumar } 4186b6b7e8aSAshish Kumar 419e84a324bSAshish Kumar int ft_board_setup(void *blob, bd_t *bd) 420e84a324bSAshish Kumar { 421e84a324bSAshish Kumar int err, i; 422e84a324bSAshish Kumar u64 base[CONFIG_NR_DRAM_BANKS]; 423e84a324bSAshish Kumar u64 size[CONFIG_NR_DRAM_BANKS]; 424e84a324bSAshish Kumar 425e84a324bSAshish Kumar ft_cpu_setup(blob, bd); 426e84a324bSAshish Kumar 427e84a324bSAshish Kumar /* fixup DT for the two GPP DDR banks */ 428e84a324bSAshish Kumar for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 429e84a324bSAshish Kumar base[i] = gd->bd->bi_dram[i].start; 430e84a324bSAshish Kumar size[i] = gd->bd->bi_dram[i].size; 431e84a324bSAshish Kumar } 432e84a324bSAshish Kumar 433e84a324bSAshish Kumar #ifdef CONFIG_RESV_RAM 434e84a324bSAshish Kumar /* reduce size if reserved memory is within this bank */ 435e84a324bSAshish Kumar if (gd->arch.resv_ram >= base[0] && 436e84a324bSAshish Kumar gd->arch.resv_ram < base[0] + size[0]) 437e84a324bSAshish Kumar size[0] = gd->arch.resv_ram - base[0]; 438e84a324bSAshish Kumar else if (gd->arch.resv_ram >= base[1] && 439e84a324bSAshish Kumar gd->arch.resv_ram < base[1] + size[1]) 440e84a324bSAshish Kumar size[1] = gd->arch.resv_ram - base[1]; 441e84a324bSAshish Kumar #endif 442e84a324bSAshish Kumar 443e84a324bSAshish Kumar fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); 444e84a324bSAshish Kumar 4456b6b7e8aSAshish Kumar fsl_fdt_fixup_flash(blob); 4466b6b7e8aSAshish Kumar 447e84a324bSAshish Kumar #ifdef CONFIG_FSL_MC_ENET 448e84a324bSAshish Kumar fdt_fixup_board_enet(blob); 449e84a324bSAshish Kumar err = fsl_mc_ldpaa_exit(bd); 450e84a324bSAshish Kumar if (err) 451e84a324bSAshish Kumar return err; 452e84a324bSAshish Kumar #endif 453e84a324bSAshish Kumar 454e84a324bSAshish Kumar return 0; 455e84a324bSAshish Kumar } 456e84a324bSAshish Kumar #endif 457*10e7eaf0SSumit Garg #endif /* defined(CONFIG_SPL_BUILD) */ 458