1 /* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <netdev.h> 10 #include <malloc.h> 11 #include <fsl_mdio.h> 12 #include <miiphy.h> 13 #include <phy.h> 14 #include <fm_eth.h> 15 #include <asm/io.h> 16 #include <exports.h> 17 #include <asm/arch/fsl_serdes.h> 18 #include <fsl-mc/ldpaa_wriop.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 #define MC_BOOT_ENV_VAR "mcinitcmd" 23 int board_eth_init(bd_t *bis) 24 { 25 #if defined(CONFIG_FSL_MC_ENET) 26 char *mc_boot_env_var; 27 int i, interface; 28 struct memac_mdio_info mdio_info; 29 struct mii_dev *dev; 30 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 31 struct memac_mdio_controller *reg; 32 u32 srds_s1, cfg; 33 34 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & 35 FSL_CHASSIS3_SRDS1_PRTCL_MASK; 36 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; 37 38 srds_s1 = serdes_get_number(FSL_SRDS_1, cfg); 39 40 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; 41 mdio_info.regs = reg; 42 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; 43 44 /* Register the EMI 1 */ 45 fm_memac_mdio_init(bis, &mdio_info); 46 47 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; 48 mdio_info.regs = reg; 49 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; 50 51 /* Register the EMI 2 */ 52 fm_memac_mdio_init(bis, &mdio_info); 53 54 switch (srds_s1) { 55 case 0x1D: 56 /* 57 * XFI does not need a PHY to work, but to avoid U-boot use 58 * default PHY address which is zero to a MAC when it found 59 * a MAC has no PHY address, we give a PHY address to XFI 60 * MAC error. 61 */ 62 wriop_set_phy_address(WRIOP1_DPMAC1, 0x0a); 63 wriop_set_phy_address(WRIOP1_DPMAC2, AQ_PHY_ADDR1); 64 wriop_set_phy_address(WRIOP1_DPMAC3, QSGMII1_PORT1_PHY_ADDR); 65 wriop_set_phy_address(WRIOP1_DPMAC4, QSGMII1_PORT2_PHY_ADDR); 66 wriop_set_phy_address(WRIOP1_DPMAC5, QSGMII1_PORT3_PHY_ADDR); 67 wriop_set_phy_address(WRIOP1_DPMAC6, QSGMII1_PORT4_PHY_ADDR); 68 wriop_set_phy_address(WRIOP1_DPMAC7, QSGMII2_PORT1_PHY_ADDR); 69 wriop_set_phy_address(WRIOP1_DPMAC8, QSGMII2_PORT2_PHY_ADDR); 70 wriop_set_phy_address(WRIOP1_DPMAC9, QSGMII2_PORT3_PHY_ADDR); 71 wriop_set_phy_address(WRIOP1_DPMAC10, QSGMII2_PORT4_PHY_ADDR); 72 73 break; 74 default: 75 printf("SerDes1 protocol 0x%x is not supported on LS1088ARDB\n", 76 srds_s1); 77 break; 78 } 79 80 for (i = WRIOP1_DPMAC3; i <= WRIOP1_DPMAC10; i++) { 81 interface = wriop_get_enet_if(i); 82 switch (interface) { 83 case PHY_INTERFACE_MODE_QSGMII: 84 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); 85 wriop_set_mdio(i, dev); 86 break; 87 default: 88 break; 89 } 90 } 91 92 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); 93 wriop_set_mdio(WRIOP1_DPMAC2, dev); 94 95 mc_boot_env_var = env_get(MC_BOOT_ENV_VAR); 96 if (mc_boot_env_var) 97 run_command_list(mc_boot_env_var, -1, 0); 98 cpu_eth_init(bis); 99 #endif /* CONFIG_FMAN_ENET */ 100 101 return pci_eth_init(bis); 102 } 103