1 /* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <netdev.h> 10 #include <malloc.h> 11 #include <fsl_mdio.h> 12 #include <miiphy.h> 13 #include <phy.h> 14 #include <fm_eth.h> 15 #include <asm/io.h> 16 #include <exports.h> 17 #include <asm/arch/fsl_serdes.h> 18 #include <fsl-mc/fsl_mc.h> 19 #include <fsl-mc/ldpaa_wriop.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 int board_eth_init(bd_t *bis) 24 { 25 #if defined(CONFIG_FSL_MC_ENET) 26 int i, interface; 27 struct memac_mdio_info mdio_info; 28 struct mii_dev *dev; 29 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 30 struct memac_mdio_controller *reg; 31 u32 srds_s1, cfg; 32 33 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & 34 FSL_CHASSIS3_SRDS1_PRTCL_MASK; 35 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; 36 37 srds_s1 = serdes_get_number(FSL_SRDS_1, cfg); 38 39 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; 40 mdio_info.regs = reg; 41 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; 42 43 /* Register the EMI 1 */ 44 fm_memac_mdio_init(bis, &mdio_info); 45 46 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; 47 mdio_info.regs = reg; 48 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; 49 50 /* Register the EMI 2 */ 51 fm_memac_mdio_init(bis, &mdio_info); 52 53 switch (srds_s1) { 54 case 0x1D: 55 /* 56 * XFI does not need a PHY to work, but to avoid U-boot use 57 * default PHY address which is zero to a MAC when it found 58 * a MAC has no PHY address, we give a PHY address to XFI 59 * MAC error. 60 */ 61 wriop_set_phy_address(WRIOP1_DPMAC1, 0x0a); 62 wriop_set_phy_address(WRIOP1_DPMAC2, AQ_PHY_ADDR1); 63 wriop_set_phy_address(WRIOP1_DPMAC3, QSGMII1_PORT1_PHY_ADDR); 64 wriop_set_phy_address(WRIOP1_DPMAC4, QSGMII1_PORT2_PHY_ADDR); 65 wriop_set_phy_address(WRIOP1_DPMAC5, QSGMII1_PORT3_PHY_ADDR); 66 wriop_set_phy_address(WRIOP1_DPMAC6, QSGMII1_PORT4_PHY_ADDR); 67 wriop_set_phy_address(WRIOP1_DPMAC7, QSGMII2_PORT1_PHY_ADDR); 68 wriop_set_phy_address(WRIOP1_DPMAC8, QSGMII2_PORT2_PHY_ADDR); 69 wriop_set_phy_address(WRIOP1_DPMAC9, QSGMII2_PORT3_PHY_ADDR); 70 wriop_set_phy_address(WRIOP1_DPMAC10, QSGMII2_PORT4_PHY_ADDR); 71 72 break; 73 default: 74 printf("SerDes1 protocol 0x%x is not supported on LS1088ARDB\n", 75 srds_s1); 76 break; 77 } 78 79 for (i = WRIOP1_DPMAC3; i <= WRIOP1_DPMAC10; i++) { 80 interface = wriop_get_enet_if(i); 81 switch (interface) { 82 case PHY_INTERFACE_MODE_QSGMII: 83 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); 84 wriop_set_mdio(i, dev); 85 break; 86 default: 87 break; 88 } 89 } 90 91 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); 92 wriop_set_mdio(WRIOP1_DPMAC2, dev); 93 94 cpu_eth_init(bis); 95 #endif /* CONFIG_FMAN_ENET */ 96 97 return pci_eth_init(bis); 98 } 99 100 #if defined(CONFIG_RESET_PHY_R) 101 void reset_phy(void) 102 { 103 mc_env_boot(); 104 } 105 #endif /* CONFIG_RESET_PHY_R */ 106