1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2017 NXP 4 */ 5 6 #include <common.h> 7 #include <command.h> 8 #include <netdev.h> 9 #include <malloc.h> 10 #include <fsl_mdio.h> 11 #include <miiphy.h> 12 #include <phy.h> 13 #include <fm_eth.h> 14 #include <asm/io.h> 15 #include <exports.h> 16 #include <asm/arch/fsl_serdes.h> 17 #include <fsl-mc/fsl_mc.h> 18 #include <fsl-mc/ldpaa_wriop.h> 19 20 int board_eth_init(bd_t *bis) 21 { 22 #if defined(CONFIG_FSL_MC_ENET) 23 int i, interface; 24 struct memac_mdio_info mdio_info; 25 struct mii_dev *dev; 26 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 27 struct memac_mdio_controller *reg; 28 u32 srds_s1, cfg; 29 30 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & 31 FSL_CHASSIS3_SRDS1_PRTCL_MASK; 32 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; 33 34 srds_s1 = serdes_get_number(FSL_SRDS_1, cfg); 35 36 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; 37 mdio_info.regs = reg; 38 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; 39 40 /* Register the EMI 1 */ 41 fm_memac_mdio_init(bis, &mdio_info); 42 43 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; 44 mdio_info.regs = reg; 45 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; 46 47 /* Register the EMI 2 */ 48 fm_memac_mdio_init(bis, &mdio_info); 49 50 switch (srds_s1) { 51 case 0x1D: 52 /* 53 * XFI does not need a PHY to work, but to avoid U-boot use 54 * default PHY address which is zero to a MAC when it found 55 * a MAC has no PHY address, we give a PHY address to XFI 56 * MAC error. 57 */ 58 wriop_set_phy_address(WRIOP1_DPMAC1, 0x0a); 59 wriop_set_phy_address(WRIOP1_DPMAC2, AQ_PHY_ADDR1); 60 wriop_set_phy_address(WRIOP1_DPMAC3, QSGMII1_PORT1_PHY_ADDR); 61 wriop_set_phy_address(WRIOP1_DPMAC4, QSGMII1_PORT2_PHY_ADDR); 62 wriop_set_phy_address(WRIOP1_DPMAC5, QSGMII1_PORT3_PHY_ADDR); 63 wriop_set_phy_address(WRIOP1_DPMAC6, QSGMII1_PORT4_PHY_ADDR); 64 wriop_set_phy_address(WRIOP1_DPMAC7, QSGMII2_PORT1_PHY_ADDR); 65 wriop_set_phy_address(WRIOP1_DPMAC8, QSGMII2_PORT2_PHY_ADDR); 66 wriop_set_phy_address(WRIOP1_DPMAC9, QSGMII2_PORT3_PHY_ADDR); 67 wriop_set_phy_address(WRIOP1_DPMAC10, QSGMII2_PORT4_PHY_ADDR); 68 69 break; 70 default: 71 printf("SerDes1 protocol 0x%x is not supported on LS1088ARDB\n", 72 srds_s1); 73 break; 74 } 75 76 for (i = WRIOP1_DPMAC3; i <= WRIOP1_DPMAC10; i++) { 77 interface = wriop_get_enet_if(i); 78 switch (interface) { 79 case PHY_INTERFACE_MODE_QSGMII: 80 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); 81 wriop_set_mdio(i, dev); 82 break; 83 default: 84 break; 85 } 86 } 87 88 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); 89 wriop_set_mdio(WRIOP1_DPMAC2, dev); 90 91 cpu_eth_init(bis); 92 #endif /* CONFIG_FMAN_ENET */ 93 94 return pci_eth_init(bis); 95 } 96 97 #if defined(CONFIG_RESET_PHY_R) 98 void reset_phy(void) 99 { 100 mc_env_boot(); 101 } 102 #endif /* CONFIG_RESET_PHY_R */ 103