1 /* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <netdev.h> 10 #include <malloc.h> 11 #include <fsl_mdio.h> 12 #include <miiphy.h> 13 #include <phy.h> 14 #include <fm_eth.h> 15 #include <asm/io.h> 16 #include <exports.h> 17 #include <asm/arch/fsl_serdes.h> 18 #include <fsl-mc/fsl_mc.h> 19 #include <fsl-mc/ldpaa_wriop.h> 20 21 int board_eth_init(bd_t *bis) 22 { 23 #if defined(CONFIG_FSL_MC_ENET) 24 int i, interface; 25 struct memac_mdio_info mdio_info; 26 struct mii_dev *dev; 27 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 28 struct memac_mdio_controller *reg; 29 u32 srds_s1, cfg; 30 31 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & 32 FSL_CHASSIS3_SRDS1_PRTCL_MASK; 33 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; 34 35 srds_s1 = serdes_get_number(FSL_SRDS_1, cfg); 36 37 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; 38 mdio_info.regs = reg; 39 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; 40 41 /* Register the EMI 1 */ 42 fm_memac_mdio_init(bis, &mdio_info); 43 44 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; 45 mdio_info.regs = reg; 46 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; 47 48 /* Register the EMI 2 */ 49 fm_memac_mdio_init(bis, &mdio_info); 50 51 switch (srds_s1) { 52 case 0x1D: 53 /* 54 * XFI does not need a PHY to work, but to avoid U-boot use 55 * default PHY address which is zero to a MAC when it found 56 * a MAC has no PHY address, we give a PHY address to XFI 57 * MAC error. 58 */ 59 wriop_set_phy_address(WRIOP1_DPMAC1, 0x0a); 60 wriop_set_phy_address(WRIOP1_DPMAC2, AQ_PHY_ADDR1); 61 wriop_set_phy_address(WRIOP1_DPMAC3, QSGMII1_PORT1_PHY_ADDR); 62 wriop_set_phy_address(WRIOP1_DPMAC4, QSGMII1_PORT2_PHY_ADDR); 63 wriop_set_phy_address(WRIOP1_DPMAC5, QSGMII1_PORT3_PHY_ADDR); 64 wriop_set_phy_address(WRIOP1_DPMAC6, QSGMII1_PORT4_PHY_ADDR); 65 wriop_set_phy_address(WRIOP1_DPMAC7, QSGMII2_PORT1_PHY_ADDR); 66 wriop_set_phy_address(WRIOP1_DPMAC8, QSGMII2_PORT2_PHY_ADDR); 67 wriop_set_phy_address(WRIOP1_DPMAC9, QSGMII2_PORT3_PHY_ADDR); 68 wriop_set_phy_address(WRIOP1_DPMAC10, QSGMII2_PORT4_PHY_ADDR); 69 70 break; 71 default: 72 printf("SerDes1 protocol 0x%x is not supported on LS1088ARDB\n", 73 srds_s1); 74 break; 75 } 76 77 for (i = WRIOP1_DPMAC3; i <= WRIOP1_DPMAC10; i++) { 78 interface = wriop_get_enet_if(i); 79 switch (interface) { 80 case PHY_INTERFACE_MODE_QSGMII: 81 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); 82 wriop_set_mdio(i, dev); 83 break; 84 default: 85 break; 86 } 87 } 88 89 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); 90 wriop_set_mdio(WRIOP1_DPMAC2, dev); 91 92 cpu_eth_init(bis); 93 #endif /* CONFIG_FMAN_ENET */ 94 95 return pci_eth_init(bis); 96 } 97 98 #if defined(CONFIG_RESET_PHY_R) 99 void reset_phy(void) 100 { 101 mc_env_boot(); 102 } 103 #endif /* CONFIG_RESET_PHY_R */ 104