1 /* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fsl_ddr_sdram.h> 9 #include <fsl_ddr_dimm_params.h> 10 #include <asm/arch/soc.h> 11 #include <asm/arch/clock.h> 12 #include "ddr.h" 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 #if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) 17 static void fsl_ddr_setup_0v9_volt(memctl_options_t *popts) 18 { 19 int vdd; 20 21 vdd = get_core_volt_from_fuse(); 22 /* Nothing to do for silicons doesn't support VID */ 23 if (vdd < 0) 24 return; 25 26 if (vdd == 900) { 27 popts->ddr_cdr1 |= DDR_CDR1_V0PT9_EN; 28 debug("VID: configure DDR to support 900 mV\n"); 29 } 30 } 31 #endif 32 33 void fsl_ddr_board_options(memctl_options_t *popts, 34 dimm_params_t *pdimm, 35 unsigned int ctrl_num) 36 { 37 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 38 ulong ddr_freq; 39 40 if (ctrl_num > 1) { 41 printf("Not supported controller number %d\n", ctrl_num); 42 return; 43 } 44 if (!pdimm->n_ranks) 45 return; 46 47 /* 48 * we use identical timing for all slots. If needed, change the code 49 * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; 50 */ 51 pbsp = udimms[0]; 52 53 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr 54 * freqency and n_banks specified in board_specific_parameters table. 55 */ 56 ddr_freq = get_ddr_freq(0) / 1000000; 57 while (pbsp->datarate_mhz_high) { 58 if (pbsp->n_ranks == pdimm->n_ranks) { 59 if (ddr_freq <= pbsp->datarate_mhz_high) { 60 popts->clk_adjust = pbsp->clk_adjust; 61 popts->wrlvl_start = pbsp->wrlvl_start; 62 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 63 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 64 goto found; 65 } 66 pbsp_highest = pbsp; 67 } 68 pbsp++; 69 } 70 71 if (pbsp_highest) { 72 printf("Error: board specific timing not found for %lu MT/s\n", 73 ddr_freq); 74 printf("Trying to use the highest speed (%u) parameters\n", 75 pbsp_highest->datarate_mhz_high); 76 popts->clk_adjust = pbsp_highest->clk_adjust; 77 popts->wrlvl_start = pbsp_highest->wrlvl_start; 78 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 79 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 80 } else { 81 panic("DIMM is not supported by this board"); 82 } 83 found: 84 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" 85 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", 86 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, 87 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, 88 pbsp->wrlvl_ctl_3); 89 90 91 92 popts->half_strength_driver_enable = 0; 93 /* 94 * Write leveling override 95 */ 96 popts->wrlvl_override = 1; 97 popts->wrlvl_sample = 0xf; 98 99 100 /* Enable ZQ calibration */ 101 popts->zq_en = 1; 102 103 /* Enable DDR hashing */ 104 popts->addr_hash = 1; 105 106 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); 107 #if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) 108 fsl_ddr_setup_0v9_volt(popts); 109 #endif 110 111 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | 112 DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; 113 } 114 115 116 int fsl_initdram(void) 117 { 118 puts("Initializing DDR....using SPD\n"); 119 120 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) 121 gd->ram_size = fsl_ddr_sdram_size(); 122 #else 123 gd->ram_size = fsl_ddr_sdram(); 124 #endif 125 return 0; 126 } 127