1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <i2c.h> 8 #include <fdt_support.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/fsl_serdes.h> 12 #include <asm/arch/ppa.h> 13 #include <asm/arch/soc.h> 14 #include <asm/arch-fsl-layerscape/fsl_icid.h> 15 #include <hwconfig.h> 16 #include <ahci.h> 17 #include <mmc.h> 18 #include <scsi.h> 19 #include <fm_eth.h> 20 #include <fsl_csu.h> 21 #include <fsl_esdhc.h> 22 #include <power/mc34vr500_pmic.h> 23 #include "cpld.h" 24 #include <fsl_sec.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 int board_early_init_f(void) 29 { 30 fsl_lsch2_early_init_f(); 31 32 return 0; 33 } 34 35 #ifndef CONFIG_SPL_BUILD 36 int checkboard(void) 37 { 38 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; 39 u8 cfg_rcw_src1, cfg_rcw_src2; 40 u16 cfg_rcw_src; 41 u8 sd1refclk_sel; 42 43 puts("Board: LS1046ARDB, boot from "); 44 45 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); 46 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); 47 cpld_rev_bit(&cfg_rcw_src1); 48 cfg_rcw_src = cfg_rcw_src1; 49 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; 50 51 if (cfg_rcw_src == 0x44) 52 printf("QSPI vBank %d\n", CPLD_READ(vbank)); 53 else if (cfg_rcw_src == 0x40) 54 puts("SD\n"); 55 else 56 puts("Invalid setting of SW5\n"); 57 58 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), 59 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); 60 61 puts("SERDES Reference Clocks:\n"); 62 sd1refclk_sel = CPLD_READ(sd1refclk_sel); 63 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); 64 65 return 0; 66 } 67 68 int board_init(void) 69 { 70 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 71 72 #ifdef CONFIG_SECURE_BOOT 73 /* 74 * In case of Secure Boot, the IBR configures the SMMU 75 * to allow only Secure transactions. 76 * SMMU must be reset in bypass mode. 77 * Set the ClientPD bit and Clear the USFCFG Bit 78 */ 79 u32 val; 80 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 81 out_le32(SMMU_SCR0, val); 82 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 83 out_le32(SMMU_NSCR0, val); 84 #endif 85 86 #ifdef CONFIG_FSL_CAAM 87 sec_init(); 88 #endif 89 90 #ifdef CONFIG_FSL_LS_PPA 91 ppa_init(); 92 #endif 93 94 /* invert AQR105 IRQ pins polarity */ 95 out_be32(&scfg->intpcr, AQR105_IRQ_MASK); 96 97 return 0; 98 } 99 100 int board_setup_core_volt(u32 vdd) 101 { 102 bool en_0v9; 103 104 en_0v9 = (vdd == 900) ? true : false; 105 cpld_select_core_volt(en_0v9); 106 107 return 0; 108 } 109 110 int get_serdes_volt(void) 111 { 112 return mc34vr500_get_sw_volt(SW4); 113 } 114 115 int set_serdes_volt(int svdd) 116 { 117 return mc34vr500_set_sw_volt(SW4, svdd); 118 } 119 120 int power_init_board(void) 121 { 122 int ret; 123 124 ret = power_mc34vr500_init(0); 125 if (ret) 126 return ret; 127 128 setup_chip_volt(); 129 130 return 0; 131 } 132 133 void config_board_mux(void) 134 { 135 #ifdef CONFIG_HAS_FSL_XHCI_USB 136 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 137 u32 usb_pwrfault; 138 139 /* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */ 140 out_be32(&scfg->rcwpmuxcr0, 0x3300); 141 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); 142 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << 143 SCFG_USBPWRFAULT_USB3_SHIFT) | 144 (SCFG_USBPWRFAULT_DEDICATED << 145 SCFG_USBPWRFAULT_USB2_SHIFT) | 146 (SCFG_USBPWRFAULT_SHARED << 147 SCFG_USBPWRFAULT_USB1_SHIFT); 148 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); 149 #endif 150 } 151 152 #ifdef CONFIG_MISC_INIT_R 153 int misc_init_r(void) 154 { 155 config_board_mux(); 156 return 0; 157 } 158 #endif 159 160 int ft_board_setup(void *blob, bd_t *bd) 161 { 162 u64 base[CONFIG_NR_DRAM_BANKS]; 163 u64 size[CONFIG_NR_DRAM_BANKS]; 164 165 /* fixup DT for the two DDR banks */ 166 base[0] = gd->bd->bi_dram[0].start; 167 size[0] = gd->bd->bi_dram[0].size; 168 base[1] = gd->bd->bi_dram[1].start; 169 size[1] = gd->bd->bi_dram[1].size; 170 171 fdt_fixup_memory_banks(blob, base, size, 2); 172 ft_cpu_setup(blob, bd); 173 174 #ifdef CONFIG_SYS_DPAA_FMAN 175 fdt_fixup_fman_ethernet(blob); 176 #endif 177 178 fdt_fixup_icid(blob); 179 180 return 0; 181 } 182 #endif 183