1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <fdt_support.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/fsl_serdes.h> 13 #include <asm/arch/ppa.h> 14 #include <asm/arch/soc.h> 15 #include <hwconfig.h> 16 #include <ahci.h> 17 #include <mmc.h> 18 #include <scsi.h> 19 #include <fm_eth.h> 20 #include <fsl_csu.h> 21 #include <fsl_esdhc.h> 22 #include <power/mc34vr500_pmic.h> 23 #include "cpld.h" 24 #include <fsl_sec.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 int board_early_init_f(void) 29 { 30 fsl_lsch2_early_init_f(); 31 32 return 0; 33 } 34 35 #ifndef CONFIG_SPL_BUILD 36 int checkboard(void) 37 { 38 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; 39 u8 cfg_rcw_src1, cfg_rcw_src2; 40 u16 cfg_rcw_src; 41 u8 sd1refclk_sel; 42 43 puts("Board: LS1046ARDB, boot from "); 44 45 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); 46 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); 47 cpld_rev_bit(&cfg_rcw_src1); 48 cfg_rcw_src = cfg_rcw_src1; 49 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; 50 51 if (cfg_rcw_src == 0x44) 52 printf("QSPI vBank %d\n", CPLD_READ(vbank)); 53 else if (cfg_rcw_src == 0x40) 54 puts("SD\n"); 55 else 56 puts("Invalid setting of SW5\n"); 57 58 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), 59 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); 60 61 puts("SERDES Reference Clocks:\n"); 62 sd1refclk_sel = CPLD_READ(sd1refclk_sel); 63 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); 64 65 return 0; 66 } 67 68 int board_init(void) 69 { 70 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 71 72 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 73 enable_layerscape_ns_access(); 74 #endif 75 76 #ifdef CONFIG_SECURE_BOOT 77 /* 78 * In case of Secure Boot, the IBR configures the SMMU 79 * to allow only Secure transactions. 80 * SMMU must be reset in bypass mode. 81 * Set the ClientPD bit and Clear the USFCFG Bit 82 */ 83 u32 val; 84 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 85 out_le32(SMMU_SCR0, val); 86 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 87 out_le32(SMMU_NSCR0, val); 88 #endif 89 90 #ifdef CONFIG_FSL_CAAM 91 sec_init(); 92 #endif 93 94 #ifdef CONFIG_FSL_LS_PPA 95 ppa_init(); 96 #endif 97 98 /* invert AQR105 IRQ pins polarity */ 99 out_be32(&scfg->intpcr, AQR105_IRQ_MASK); 100 101 return 0; 102 } 103 104 int board_setup_core_volt(u32 vdd) 105 { 106 bool en_0v9; 107 108 en_0v9 = (vdd == 900) ? true : false; 109 cpld_select_core_volt(en_0v9); 110 111 return 0; 112 } 113 114 int get_serdes_volt(void) 115 { 116 return mc34vr500_get_sw_volt(SW4); 117 } 118 119 int set_serdes_volt(int svdd) 120 { 121 return mc34vr500_set_sw_volt(SW4, svdd); 122 } 123 124 int power_init_board(void) 125 { 126 int ret; 127 128 ret = power_mc34vr500_init(0); 129 if (ret) 130 return ret; 131 132 setup_chip_volt(); 133 134 return 0; 135 } 136 137 void config_board_mux(void) 138 { 139 #ifdef CONFIG_HAS_FSL_XHCI_USB 140 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 141 u32 usb_pwrfault; 142 143 /* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */ 144 out_be32(&scfg->rcwpmuxcr0, 0x3300); 145 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); 146 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << 147 SCFG_USBPWRFAULT_USB3_SHIFT) | 148 (SCFG_USBPWRFAULT_DEDICATED << 149 SCFG_USBPWRFAULT_USB2_SHIFT) | 150 (SCFG_USBPWRFAULT_SHARED << 151 SCFG_USBPWRFAULT_USB1_SHIFT); 152 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); 153 #endif 154 } 155 156 #ifdef CONFIG_MISC_INIT_R 157 int misc_init_r(void) 158 { 159 config_board_mux(); 160 return 0; 161 } 162 #endif 163 164 int ft_board_setup(void *blob, bd_t *bd) 165 { 166 u64 base[CONFIG_NR_DRAM_BANKS]; 167 u64 size[CONFIG_NR_DRAM_BANKS]; 168 169 /* fixup DT for the two DDR banks */ 170 base[0] = gd->bd->bi_dram[0].start; 171 size[0] = gd->bd->bi_dram[0].size; 172 base[1] = gd->bd->bi_dram[1].start; 173 size[1] = gd->bd->bi_dram[1].size; 174 175 fdt_fixup_memory_banks(blob, base, size, 2); 176 ft_cpu_setup(blob, bd); 177 178 #ifdef CONFIG_SYS_DPAA_FMAN 179 fdt_fixup_fman_ethernet(blob); 180 #endif 181 182 return 0; 183 } 184 #endif 185