1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <fdt_support.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/fsl_serdes.h> 13 #include <asm/arch/ppa.h> 14 #include <asm/arch/soc.h> 15 #include <hwconfig.h> 16 #include <ahci.h> 17 #include <mmc.h> 18 #include <scsi.h> 19 #include <fm_eth.h> 20 #include <fsl_csu.h> 21 #include <fsl_esdhc.h> 22 #include <power/mc34vr500_pmic.h> 23 #include "cpld.h" 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 int board_early_init_f(void) 28 { 29 fsl_lsch2_early_init_f(); 30 31 return 0; 32 } 33 34 #ifndef CONFIG_SPL_BUILD 35 int checkboard(void) 36 { 37 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; 38 u8 cfg_rcw_src1, cfg_rcw_src2; 39 u16 cfg_rcw_src; 40 u8 sd1refclk_sel; 41 42 puts("Board: LS1046ARDB, boot from "); 43 44 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); 45 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); 46 cpld_rev_bit(&cfg_rcw_src1); 47 cfg_rcw_src = cfg_rcw_src1; 48 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; 49 50 if (cfg_rcw_src == 0x44) 51 printf("QSPI vBank %d\n", CPLD_READ(vbank)); 52 else if (cfg_rcw_src == 0x40) 53 puts("SD\n"); 54 else 55 puts("Invalid setting of SW5\n"); 56 57 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), 58 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); 59 60 puts("SERDES Reference Clocks:\n"); 61 sd1refclk_sel = CPLD_READ(sd1refclk_sel); 62 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); 63 64 return 0; 65 } 66 67 int board_init(void) 68 { 69 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 70 71 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 72 enable_layerscape_ns_access(); 73 #endif 74 75 #ifdef CONFIG_FSL_LS_PPA 76 ppa_init(); 77 #endif 78 79 /* invert AQR105 IRQ pins polarity */ 80 out_be32(&scfg->intpcr, AQR105_IRQ_MASK); 81 82 return 0; 83 } 84 85 int board_setup_core_volt(u32 vdd) 86 { 87 bool en_0v9; 88 89 en_0v9 = (vdd == 900) ? true : false; 90 cpld_select_core_volt(en_0v9); 91 92 return 0; 93 } 94 95 int get_serdes_volt(void) 96 { 97 return mc34vr500_get_sw_volt(SW4); 98 } 99 100 int set_serdes_volt(int svdd) 101 { 102 return mc34vr500_set_sw_volt(SW4, svdd); 103 } 104 105 int power_init_board(void) 106 { 107 int ret; 108 109 ret = power_mc34vr500_init(0); 110 if (ret) 111 return ret; 112 113 setup_chip_volt(); 114 115 return 0; 116 } 117 118 void config_board_mux(void) 119 { 120 #ifdef CONFIG_HAS_FSL_XHCI_USB 121 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 122 u32 usb_pwrfault; 123 124 /* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */ 125 out_be32(&scfg->rcwpmuxcr0, 0x3300); 126 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); 127 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << 128 SCFG_USBPWRFAULT_USB3_SHIFT) | 129 (SCFG_USBPWRFAULT_DEDICATED << 130 SCFG_USBPWRFAULT_USB2_SHIFT) | 131 (SCFG_USBPWRFAULT_SHARED << 132 SCFG_USBPWRFAULT_USB1_SHIFT); 133 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); 134 #endif 135 } 136 137 #ifdef CONFIG_MISC_INIT_R 138 int misc_init_r(void) 139 { 140 config_board_mux(); 141 return 0; 142 } 143 #endif 144 145 int ft_board_setup(void *blob, bd_t *bd) 146 { 147 u64 base[CONFIG_NR_DRAM_BANKS]; 148 u64 size[CONFIG_NR_DRAM_BANKS]; 149 150 /* fixup DT for the two DDR banks */ 151 base[0] = gd->bd->bi_dram[0].start; 152 size[0] = gd->bd->bi_dram[0].size; 153 base[1] = gd->bd->bi_dram[1].start; 154 size[1] = gd->bd->bi_dram[1].size; 155 156 fdt_fixup_memory_banks(blob, base, size, 2); 157 ft_cpu_setup(blob, bd); 158 159 #ifdef CONFIG_SYS_DPAA_FMAN 160 fdt_fixup_fman_ethernet(blob); 161 #endif 162 163 return 0; 164 } 165 #endif 166