1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <fdt_support.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/fsl_serdes.h> 13 #include <asm/arch/ppa.h> 14 #include <asm/arch/soc.h> 15 #include <hwconfig.h> 16 #include <ahci.h> 17 #include <mmc.h> 18 #include <scsi.h> 19 #include <fm_eth.h> 20 #include <fsl_csu.h> 21 #include <fsl_esdhc.h> 22 #include "cpld.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 int checkboard(void) 27 { 28 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; 29 u8 cfg_rcw_src1, cfg_rcw_src2; 30 u16 cfg_rcw_src; 31 u8 sd1refclk_sel; 32 33 puts("Board: LS1046ARDB, boot from "); 34 35 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); 36 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); 37 cpld_rev_bit(&cfg_rcw_src1); 38 cfg_rcw_src = cfg_rcw_src1; 39 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; 40 41 if (cfg_rcw_src == 0x44) 42 printf("QSPI vBank %d\n", CPLD_READ(vbank)); 43 else if (cfg_rcw_src == 0x40) 44 puts("SD\n"); 45 else 46 puts("Invalid setting of SW5\n"); 47 48 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), 49 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); 50 51 puts("SERDES Reference Clocks:\n"); 52 sd1refclk_sel = CPLD_READ(sd1refclk_sel); 53 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); 54 55 return 0; 56 } 57 58 int dram_init(void) 59 { 60 gd->ram_size = initdram(0); 61 62 return 0; 63 } 64 65 int board_early_init_f(void) 66 { 67 fsl_lsch2_early_init_f(); 68 69 return 0; 70 } 71 72 int board_init(void) 73 { 74 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 75 76 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 77 enable_layerscape_ns_access(); 78 #endif 79 80 #ifdef CONFIG_FSL_LS_PPA 81 ppa_init(); 82 #endif 83 84 /* invert AQR105 IRQ pins polarity */ 85 out_be32(&scfg->intpcr, AQR105_IRQ_MASK); 86 87 return 0; 88 } 89 90 void config_board_mux(void) 91 { 92 #ifdef CONFIG_HAS_FSL_XHCI_USB 93 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 94 u32 usb_pwrfault; 95 96 /* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */ 97 out_be32(&scfg->rcwpmuxcr0, 0x3300); 98 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); 99 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << 100 SCFG_USBPWRFAULT_USB3_SHIFT) | 101 (SCFG_USBPWRFAULT_DEDICATED << 102 SCFG_USBPWRFAULT_USB2_SHIFT) | 103 (SCFG_USBPWRFAULT_SHARED << 104 SCFG_USBPWRFAULT_USB1_SHIFT); 105 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); 106 #endif 107 } 108 109 #ifdef CONFIG_MISC_INIT_R 110 int misc_init_r(void) 111 { 112 config_board_mux(); 113 return 0; 114 } 115 #endif 116 117 int ft_board_setup(void *blob, bd_t *bd) 118 { 119 u64 base[CONFIG_NR_DRAM_BANKS]; 120 u64 size[CONFIG_NR_DRAM_BANKS]; 121 122 /* fixup DT for the two DDR banks */ 123 base[0] = gd->bd->bi_dram[0].start; 124 size[0] = gd->bd->bi_dram[0].size; 125 base[1] = gd->bd->bi_dram[1].start; 126 size[1] = gd->bd->bi_dram[1].size; 127 128 fdt_fixup_memory_banks(blob, base, size, 2); 129 ft_cpu_setup(blob, bd); 130 131 #ifdef CONFIG_SYS_DPAA_FMAN 132 fdt_fixup_fman_ethernet(blob); 133 #endif 134 135 return 0; 136 } 137