1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <fdt_support.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/fsl_serdes.h> 13 #include <asm/arch/ppa.h> 14 #include <asm/arch/soc.h> 15 #include <hwconfig.h> 16 #include <ahci.h> 17 #include <mmc.h> 18 #include <scsi.h> 19 #include <fm_eth.h> 20 #include <fsl_csu.h> 21 #include <fsl_esdhc.h> 22 #include <power/mc34vr500_pmic.h> 23 #include "cpld.h" 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 int checkboard(void) 28 { 29 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; 30 u8 cfg_rcw_src1, cfg_rcw_src2; 31 u16 cfg_rcw_src; 32 u8 sd1refclk_sel; 33 34 puts("Board: LS1046ARDB, boot from "); 35 36 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); 37 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); 38 cpld_rev_bit(&cfg_rcw_src1); 39 cfg_rcw_src = cfg_rcw_src1; 40 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; 41 42 if (cfg_rcw_src == 0x44) 43 printf("QSPI vBank %d\n", CPLD_READ(vbank)); 44 else if (cfg_rcw_src == 0x40) 45 puts("SD\n"); 46 else 47 puts("Invalid setting of SW5\n"); 48 49 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), 50 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); 51 52 puts("SERDES Reference Clocks:\n"); 53 sd1refclk_sel = CPLD_READ(sd1refclk_sel); 54 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); 55 56 return 0; 57 } 58 59 int dram_init(void) 60 { 61 gd->ram_size = initdram(0); 62 63 return 0; 64 } 65 66 int board_early_init_f(void) 67 { 68 fsl_lsch2_early_init_f(); 69 70 return 0; 71 } 72 73 int board_init(void) 74 { 75 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 76 77 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 78 enable_layerscape_ns_access(); 79 #endif 80 81 #ifdef CONFIG_FSL_LS_PPA 82 ppa_init(); 83 #endif 84 85 /* invert AQR105 IRQ pins polarity */ 86 out_be32(&scfg->intpcr, AQR105_IRQ_MASK); 87 88 return 0; 89 } 90 91 int board_setup_core_volt(u32 vdd) 92 { 93 bool en_0v9; 94 95 en_0v9 = (vdd == 900) ? true : false; 96 cpld_select_core_volt(en_0v9); 97 98 return 0; 99 } 100 101 int get_serdes_volt(void) 102 { 103 return mc34vr500_get_sw_volt(SW4); 104 } 105 106 int set_serdes_volt(int svdd) 107 { 108 return mc34vr500_set_sw_volt(SW4, svdd); 109 } 110 111 int power_init_board(void) 112 { 113 int ret; 114 115 ret = power_mc34vr500_init(0); 116 if (ret) 117 return ret; 118 119 setup_chip_volt(); 120 121 return 0; 122 } 123 124 void config_board_mux(void) 125 { 126 #ifdef CONFIG_HAS_FSL_XHCI_USB 127 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 128 u32 usb_pwrfault; 129 130 /* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */ 131 out_be32(&scfg->rcwpmuxcr0, 0x3300); 132 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); 133 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << 134 SCFG_USBPWRFAULT_USB3_SHIFT) | 135 (SCFG_USBPWRFAULT_DEDICATED << 136 SCFG_USBPWRFAULT_USB2_SHIFT) | 137 (SCFG_USBPWRFAULT_SHARED << 138 SCFG_USBPWRFAULT_USB1_SHIFT); 139 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); 140 #endif 141 } 142 143 #ifdef CONFIG_MISC_INIT_R 144 int misc_init_r(void) 145 { 146 config_board_mux(); 147 return 0; 148 } 149 #endif 150 151 int ft_board_setup(void *blob, bd_t *bd) 152 { 153 u64 base[CONFIG_NR_DRAM_BANKS]; 154 u64 size[CONFIG_NR_DRAM_BANKS]; 155 156 /* fixup DT for the two DDR banks */ 157 base[0] = gd->bd->bi_dram[0].start; 158 size[0] = gd->bd->bi_dram[0].size; 159 base[1] = gd->bd->bi_dram[1].start; 160 size[1] = gd->bd->bi_dram[1].size; 161 162 fdt_fixup_memory_banks(blob, base, size, 2); 163 ft_cpu_setup(blob, bd); 164 165 #ifdef CONFIG_SYS_DPAA_FMAN 166 fdt_fixup_fman_ethernet(blob); 167 #endif 168 169 return 0; 170 } 171