1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2dd02936fSMingkai Hu /* 3dd02936fSMingkai Hu * Copyright 2016 Freescale Semiconductor, Inc. 4dd02936fSMingkai Hu */ 5dd02936fSMingkai Hu 6dd02936fSMingkai Hu #include <common.h> 7dd02936fSMingkai Hu #include <i2c.h> 8dd02936fSMingkai Hu #include <fdt_support.h> 9dd02936fSMingkai Hu #include <asm/io.h> 10dd02936fSMingkai Hu #include <asm/arch/clock.h> 11dd02936fSMingkai Hu #include <asm/arch/fsl_serdes.h> 12dd02936fSMingkai Hu #include <asm/arch/ppa.h> 13dd02936fSMingkai Hu #include <asm/arch/soc.h> 14dd02936fSMingkai Hu #include <hwconfig.h> 15dd02936fSMingkai Hu #include <ahci.h> 16dd02936fSMingkai Hu #include <mmc.h> 17dd02936fSMingkai Hu #include <scsi.h> 18dd02936fSMingkai Hu #include <fm_eth.h> 19dd02936fSMingkai Hu #include <fsl_csu.h> 20dd02936fSMingkai Hu #include <fsl_esdhc.h> 21dccef2ecSHou Zhiqiang #include <power/mc34vr500_pmic.h> 22dd02936fSMingkai Hu #include "cpld.h" 23f7244f2cSVinitha Pillai-B57223 #include <fsl_sec.h> 24dd02936fSMingkai Hu 25dd02936fSMingkai Hu DECLARE_GLOBAL_DATA_PTR; 26dd02936fSMingkai Hu 27a52ff334SSumit Garg int board_early_init_f(void) 28a52ff334SSumit Garg { 29a52ff334SSumit Garg fsl_lsch2_early_init_f(); 30a52ff334SSumit Garg 31a52ff334SSumit Garg return 0; 32a52ff334SSumit Garg } 33a52ff334SSumit Garg 34a52ff334SSumit Garg #ifndef CONFIG_SPL_BUILD 35dd02936fSMingkai Hu int checkboard(void) 36dd02936fSMingkai Hu { 37dd02936fSMingkai Hu static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; 38dd02936fSMingkai Hu u8 cfg_rcw_src1, cfg_rcw_src2; 39dd02936fSMingkai Hu u16 cfg_rcw_src; 40dd02936fSMingkai Hu u8 sd1refclk_sel; 41dd02936fSMingkai Hu 42dd02936fSMingkai Hu puts("Board: LS1046ARDB, boot from "); 43dd02936fSMingkai Hu 44dd02936fSMingkai Hu cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); 45dd02936fSMingkai Hu cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); 46dd02936fSMingkai Hu cpld_rev_bit(&cfg_rcw_src1); 47dd02936fSMingkai Hu cfg_rcw_src = cfg_rcw_src1; 48dd02936fSMingkai Hu cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; 49dd02936fSMingkai Hu 50dd02936fSMingkai Hu if (cfg_rcw_src == 0x44) 51dd02936fSMingkai Hu printf("QSPI vBank %d\n", CPLD_READ(vbank)); 52dd02936fSMingkai Hu else if (cfg_rcw_src == 0x40) 53dd02936fSMingkai Hu puts("SD\n"); 54dd02936fSMingkai Hu else 55dd02936fSMingkai Hu puts("Invalid setting of SW5\n"); 56dd02936fSMingkai Hu 57dd02936fSMingkai Hu printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), 58dd02936fSMingkai Hu CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); 59dd02936fSMingkai Hu 60dd02936fSMingkai Hu puts("SERDES Reference Clocks:\n"); 61dd02936fSMingkai Hu sd1refclk_sel = CPLD_READ(sd1refclk_sel); 62dd02936fSMingkai Hu printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); 63dd02936fSMingkai Hu 64dd02936fSMingkai Hu return 0; 65dd02936fSMingkai Hu } 66dd02936fSMingkai Hu 67dd02936fSMingkai Hu int board_init(void) 68dd02936fSMingkai Hu { 69dd02936fSMingkai Hu struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 70dd02936fSMingkai Hu 71f7244f2cSVinitha Pillai-B57223 #ifdef CONFIG_SECURE_BOOT 72f7244f2cSVinitha Pillai-B57223 /* 73f7244f2cSVinitha Pillai-B57223 * In case of Secure Boot, the IBR configures the SMMU 74f7244f2cSVinitha Pillai-B57223 * to allow only Secure transactions. 75f7244f2cSVinitha Pillai-B57223 * SMMU must be reset in bypass mode. 76f7244f2cSVinitha Pillai-B57223 * Set the ClientPD bit and Clear the USFCFG Bit 77f7244f2cSVinitha Pillai-B57223 */ 78f7244f2cSVinitha Pillai-B57223 u32 val; 79f7244f2cSVinitha Pillai-B57223 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 80f7244f2cSVinitha Pillai-B57223 out_le32(SMMU_SCR0, val); 81f7244f2cSVinitha Pillai-B57223 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 82f7244f2cSVinitha Pillai-B57223 out_le32(SMMU_NSCR0, val); 83f7244f2cSVinitha Pillai-B57223 #endif 84f7244f2cSVinitha Pillai-B57223 85f7244f2cSVinitha Pillai-B57223 #ifdef CONFIG_FSL_CAAM 86f7244f2cSVinitha Pillai-B57223 sec_init(); 87f7244f2cSVinitha Pillai-B57223 #endif 88f7244f2cSVinitha Pillai-B57223 89dd02936fSMingkai Hu #ifdef CONFIG_FSL_LS_PPA 90dd02936fSMingkai Hu ppa_init(); 91dd02936fSMingkai Hu #endif 92dd02936fSMingkai Hu 93dd02936fSMingkai Hu /* invert AQR105 IRQ pins polarity */ 94dd02936fSMingkai Hu out_be32(&scfg->intpcr, AQR105_IRQ_MASK); 95dd02936fSMingkai Hu 96dd02936fSMingkai Hu return 0; 97dd02936fSMingkai Hu } 98dd02936fSMingkai Hu 99dccef2ecSHou Zhiqiang int board_setup_core_volt(u32 vdd) 100dccef2ecSHou Zhiqiang { 101dccef2ecSHou Zhiqiang bool en_0v9; 102dccef2ecSHou Zhiqiang 103dccef2ecSHou Zhiqiang en_0v9 = (vdd == 900) ? true : false; 104dccef2ecSHou Zhiqiang cpld_select_core_volt(en_0v9); 105dccef2ecSHou Zhiqiang 106dccef2ecSHou Zhiqiang return 0; 107dccef2ecSHou Zhiqiang } 108dccef2ecSHou Zhiqiang 109dccef2ecSHou Zhiqiang int get_serdes_volt(void) 110dccef2ecSHou Zhiqiang { 111dccef2ecSHou Zhiqiang return mc34vr500_get_sw_volt(SW4); 112dccef2ecSHou Zhiqiang } 113dccef2ecSHou Zhiqiang 114dccef2ecSHou Zhiqiang int set_serdes_volt(int svdd) 115dccef2ecSHou Zhiqiang { 116dccef2ecSHou Zhiqiang return mc34vr500_set_sw_volt(SW4, svdd); 117dccef2ecSHou Zhiqiang } 118dccef2ecSHou Zhiqiang 119dccef2ecSHou Zhiqiang int power_init_board(void) 120dccef2ecSHou Zhiqiang { 121dccef2ecSHou Zhiqiang int ret; 122dccef2ecSHou Zhiqiang 123dccef2ecSHou Zhiqiang ret = power_mc34vr500_init(0); 124dccef2ecSHou Zhiqiang if (ret) 125dccef2ecSHou Zhiqiang return ret; 126dccef2ecSHou Zhiqiang 127dccef2ecSHou Zhiqiang setup_chip_volt(); 128dccef2ecSHou Zhiqiang 129dccef2ecSHou Zhiqiang return 0; 130dccef2ecSHou Zhiqiang } 131dccef2ecSHou Zhiqiang 132dd02936fSMingkai Hu void config_board_mux(void) 133dd02936fSMingkai Hu { 134dd02936fSMingkai Hu #ifdef CONFIG_HAS_FSL_XHCI_USB 135dd02936fSMingkai Hu struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 136dd02936fSMingkai Hu u32 usb_pwrfault; 137dd02936fSMingkai Hu 138dd02936fSMingkai Hu /* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */ 139dd02936fSMingkai Hu out_be32(&scfg->rcwpmuxcr0, 0x3300); 140dd02936fSMingkai Hu out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); 141dd02936fSMingkai Hu usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << 142dd02936fSMingkai Hu SCFG_USBPWRFAULT_USB3_SHIFT) | 143dd02936fSMingkai Hu (SCFG_USBPWRFAULT_DEDICATED << 144dd02936fSMingkai Hu SCFG_USBPWRFAULT_USB2_SHIFT) | 145dd02936fSMingkai Hu (SCFG_USBPWRFAULT_SHARED << 146dd02936fSMingkai Hu SCFG_USBPWRFAULT_USB1_SHIFT); 147dd02936fSMingkai Hu out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); 148dd02936fSMingkai Hu #endif 149dd02936fSMingkai Hu } 150dd02936fSMingkai Hu 151dd02936fSMingkai Hu #ifdef CONFIG_MISC_INIT_R 152dd02936fSMingkai Hu int misc_init_r(void) 153dd02936fSMingkai Hu { 154dd02936fSMingkai Hu config_board_mux(); 155dd02936fSMingkai Hu return 0; 156dd02936fSMingkai Hu } 157dd02936fSMingkai Hu #endif 158dd02936fSMingkai Hu 159dd02936fSMingkai Hu int ft_board_setup(void *blob, bd_t *bd) 160dd02936fSMingkai Hu { 161dd02936fSMingkai Hu u64 base[CONFIG_NR_DRAM_BANKS]; 162dd02936fSMingkai Hu u64 size[CONFIG_NR_DRAM_BANKS]; 163dd02936fSMingkai Hu 164dd02936fSMingkai Hu /* fixup DT for the two DDR banks */ 165dd02936fSMingkai Hu base[0] = gd->bd->bi_dram[0].start; 166dd02936fSMingkai Hu size[0] = gd->bd->bi_dram[0].size; 167dd02936fSMingkai Hu base[1] = gd->bd->bi_dram[1].start; 168dd02936fSMingkai Hu size[1] = gd->bd->bi_dram[1].size; 169dd02936fSMingkai Hu 170dd02936fSMingkai Hu fdt_fixup_memory_banks(blob, base, size, 2); 171dd02936fSMingkai Hu ft_cpu_setup(blob, bd); 172dd02936fSMingkai Hu 173dd02936fSMingkai Hu #ifdef CONFIG_SYS_DPAA_FMAN 174dd02936fSMingkai Hu fdt_fixup_fman_ethernet(blob); 175dd02936fSMingkai Hu #endif 176dd02936fSMingkai Hu 177dd02936fSMingkai Hu return 0; 178dd02936fSMingkai Hu } 179a52ff334SSumit Garg #endif 180