1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2016 Freescale Semiconductor, Inc.
4  */
5 #include <common.h>
6 #include <asm/io.h>
7 #include <netdev.h>
8 #include <fm_eth.h>
9 #include <fsl_dtsec.h>
10 #include <fsl_mdio.h>
11 #include <malloc.h>
12 
13 #include "../common/fman.h"
14 
15 int board_eth_init(bd_t *bis)
16 {
17 #ifdef CONFIG_FMAN_ENET
18 	int i;
19 	struct memac_mdio_info dtsec_mdio_info;
20 	struct memac_mdio_info tgec_mdio_info;
21 	struct mii_dev *dev;
22 	u32 srds_s1;
23 	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
24 
25 	srds_s1 = in_be32(&gur->rcwsr[4]) &
26 			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
27 	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
28 
29 	dtsec_mdio_info.regs =
30 		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
31 
32 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
33 
34 	/* Register the 1G MDIO bus */
35 	fm_memac_mdio_init(bis, &dtsec_mdio_info);
36 
37 	tgec_mdio_info.regs =
38 		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
39 	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
40 
41 	/* Register the 10G MDIO bus */
42 	fm_memac_mdio_init(bis, &tgec_mdio_info);
43 
44 	/* Set the two on-board RGMII PHY address */
45 	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
46 	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
47 
48 	/* Set the two on-board SGMII PHY address */
49 	fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR);
50 	fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR);
51 
52 	/* Set the on-board AQ PHY address */
53 	fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
54 
55 	switch (srds_s1) {
56 	case 0x1133:
57 		break;
58 	default:
59 		printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n",
60 		       srds_s1);
61 		break;
62 	}
63 
64 	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
65 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
66 		fm_info_set_mdio(i, dev);
67 
68 	/* XFI on lane A, MAC 9 */
69 	dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
70 	fm_info_set_mdio(FM1_10GEC1, dev);
71 
72 	cpu_eth_init(bis);
73 #endif
74 
75 	return pci_eth_init(bis);
76 }
77 
78 #ifdef CONFIG_FMAN_ENET
79 int fdt_update_ethernet_dt(void *blob)
80 {
81 	u32 srds_s1;
82 	int i, prop;
83 	int offset, nodeoff;
84 	const char *path;
85 	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
86 
87 	srds_s1 = in_be32(&gur->rcwsr[4]) &
88 			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
89 	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
90 
91 	/* Cycle through all aliases */
92 	for (prop = 0; ; prop++) {
93 		const char *name;
94 
95 		/* FDT might have been edited, recompute the offset */
96 		offset = fdt_first_property_offset(blob,
97 						   fdt_path_offset(blob,
98 								   "/aliases")
99 						   );
100 		/* Select property number 'prop' */
101 		for (i = 0; i < prop; i++)
102 			offset = fdt_next_property_offset(blob, offset);
103 
104 		if (offset < 0)
105 			break;
106 
107 		path = fdt_getprop_by_offset(blob, offset, &name, NULL);
108 		nodeoff = fdt_path_offset(blob, path);
109 
110 		switch (srds_s1) {
111 		case 0x1133:
112 			if (!strcmp(name, "ethernet0"))
113 				fdt_status_disabled(blob, nodeoff);
114 
115 			if (!strcmp(name, "ethernet1"))
116 				fdt_status_disabled(blob, nodeoff);
117 		break;
118 		default:
119 			printf("%s: Invalid SerDes prtcl 0x%x for LS1046ARDB\n",
120 			       __func__, srds_s1);
121 		break;
122 		}
123 	}
124 
125 	return 0;
126 }
127 #endif
128