1 /*
2  * Copyright 2016 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __DDR_H__
8 #define __DDR_H__
9 
10 void erratum_a008850_post(void);
11 
12 struct board_specific_parameters {
13 	u32 n_ranks;
14 	u32 datarate_mhz_high;
15 	u32 rank_gb;
16 	u32 clk_adjust;
17 	u32 wrlvl_start;
18 	u32 wrlvl_ctl_2;
19 	u32 wrlvl_ctl_3;
20 };
21 
22 /*
23  * These tables contain all valid speeds we want to override with board
24  * specific parameters. datarate_mhz_high values need to be in ascending order
25  * for each n_ranks group.
26  */
27 static const struct board_specific_parameters udimm0[] = {
28 	/*
29 	 * memory controller 0
30 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
31 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
32 	 */
33 	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
34 	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
35 	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
36 	{2,  2300, 0, 8,     9, 0x0A0B0C10, 0x1213140E,},
37 	{}
38 };
39 
40 static const struct board_specific_parameters *udimms[] = {
41 	udimm0,
42 };
43 
44 static const struct board_specific_parameters rdimm0[] = {
45 	/*
46 	 * memory controller 0
47 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
48 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
49 	 */
50 	{2,  1666, 0, 0x8,     0x0D, 0x0C0B0A08, 0x0A0B0C08,},
51 	{2,  1900, 0, 0x8,     0x0E, 0x0D0C0B09, 0x0B0C0D09,},
52 	{2,  2300, 0, 0xa,     0x12, 0x100F0D0C, 0x0E0F100C,},
53 	{1,  1666, 0, 0x8,     0x0D, 0x0C0B0A08, 0x0A0B0C08,},
54 	{1,  1900, 0, 0x8,     0x0E, 0x0D0C0B09, 0x0B0C0D09,},
55 	{1,  2300, 0, 0xa,     0x12, 0x100F0D0C, 0x0E0F100C,},
56 	{}
57 };
58 
59 static const struct board_specific_parameters *rdimms[] = {
60 	rdimm0,
61 };
62 
63 #endif
64