1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <fdt_support.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/fsl_serdes.h> 13 #include <asm/arch/fdt.h> 14 #include <asm/arch/soc.h> 15 #include <ahci.h> 16 #include <hwconfig.h> 17 #include <mmc.h> 18 #include <scsi.h> 19 #include <fm_eth.h> 20 #include <fsl_csu.h> 21 #include <fsl_esdhc.h> 22 #include <fsl_ifc.h> 23 #include <spl.h> 24 25 #include "../common/vid.h" 26 #include "../common/qixis.h" 27 #include "ls1046aqds_qixis.h" 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 enum { 32 MUX_TYPE_GPIO, 33 }; 34 35 int checkboard(void) 36 { 37 char buf[64]; 38 #ifndef CONFIG_SD_BOOT 39 u8 sw; 40 #endif 41 42 puts("Board: LS1046AQDS, boot from "); 43 44 #ifdef CONFIG_SD_BOOT 45 puts("SD\n"); 46 #else 47 sw = QIXIS_READ(brdcfg[0]); 48 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 49 50 if (sw < 0x8) 51 printf("vBank: %d\n", sw); 52 else if (sw == 0x8) 53 puts("PromJet\n"); 54 else if (sw == 0x9) 55 puts("NAND\n"); 56 else if (sw == 0xF) 57 printf("QSPI\n"); 58 else 59 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 60 #endif 61 62 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", 63 QIXIS_READ(id), QIXIS_READ(arch)); 64 65 printf("FPGA: v%d (%s), build %d\n", 66 (int)QIXIS_READ(scver), qixis_read_tag(buf), 67 (int)qixis_read_minor()); 68 69 return 0; 70 } 71 72 bool if_board_diff_clk(void) 73 { 74 u8 diff_conf = QIXIS_READ(brdcfg[11]); 75 76 return diff_conf & 0x40; 77 } 78 79 unsigned long get_board_sys_clk(void) 80 { 81 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 82 83 switch (sysclk_conf & 0x0f) { 84 case QIXIS_SYSCLK_64: 85 return 64000000; 86 case QIXIS_SYSCLK_83: 87 return 83333333; 88 case QIXIS_SYSCLK_100: 89 return 100000000; 90 case QIXIS_SYSCLK_125: 91 return 125000000; 92 case QIXIS_SYSCLK_133: 93 return 133333333; 94 case QIXIS_SYSCLK_150: 95 return 150000000; 96 case QIXIS_SYSCLK_160: 97 return 160000000; 98 case QIXIS_SYSCLK_166: 99 return 166666666; 100 } 101 102 return 66666666; 103 } 104 105 unsigned long get_board_ddr_clk(void) 106 { 107 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 108 109 if (if_board_diff_clk()) 110 return get_board_sys_clk(); 111 switch ((ddrclk_conf & 0x30) >> 4) { 112 case QIXIS_DDRCLK_100: 113 return 100000000; 114 case QIXIS_DDRCLK_125: 115 return 125000000; 116 case QIXIS_DDRCLK_133: 117 return 133333333; 118 } 119 120 return 66666666; 121 } 122 123 int select_i2c_ch_pca9547(u8 ch) 124 { 125 int ret; 126 127 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 128 if (ret) { 129 puts("PCA: failed to select proper channel\n"); 130 return ret; 131 } 132 133 return 0; 134 } 135 136 int dram_init(void) 137 { 138 /* 139 * When resuming from deep sleep, the I2C channel may not be 140 * in the default channel. So, switch to the default channel 141 * before accessing DDR SPD. 142 */ 143 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 144 gd->ram_size = initdram(0); 145 146 return 0; 147 } 148 149 int i2c_multiplexer_select_vid_channel(u8 channel) 150 { 151 return select_i2c_ch_pca9547(channel); 152 } 153 154 int board_early_init_f(void) 155 { 156 #ifdef CONFIG_HAS_FSL_XHCI_USB 157 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 158 u32 usb_pwrfault; 159 #endif 160 161 #ifdef CONFIG_SYS_I2C_EARLY_INIT 162 i2c_early_init_f(); 163 #endif 164 fsl_lsch2_early_init_f(); 165 166 #ifdef CONFIG_HAS_FSL_XHCI_USB 167 out_be32(&scfg->rcwpmuxcr0, 0x3333); 168 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); 169 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << 170 SCFG_USBPWRFAULT_USB3_SHIFT) | 171 (SCFG_USBPWRFAULT_DEDICATED << 172 SCFG_USBPWRFAULT_USB2_SHIFT) | 173 (SCFG_USBPWRFAULT_SHARED << 174 SCFG_USBPWRFAULT_USB1_SHIFT); 175 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); 176 #endif 177 178 return 0; 179 } 180 181 #ifdef CONFIG_FSL_DEEP_SLEEP 182 /* determine if it is a warm boot */ 183 bool is_warm_boot(void) 184 { 185 #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) 186 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 187 188 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) 189 return 1; 190 191 return 0; 192 } 193 #endif 194 195 int config_board_mux(int ctrl_type) 196 { 197 u8 reg14; 198 199 reg14 = QIXIS_READ(brdcfg[14]); 200 201 switch (ctrl_type) { 202 case MUX_TYPE_GPIO: 203 reg14 = (reg14 & (~0x6)) | 0x2; 204 break; 205 default: 206 puts("Unsupported mux interface type\n"); 207 return -1; 208 } 209 210 QIXIS_WRITE(brdcfg[14], reg14); 211 212 return 0; 213 } 214 215 int config_serdes_mux(void) 216 { 217 return 0; 218 } 219 220 #ifdef CONFIG_MISC_INIT_R 221 int misc_init_r(void) 222 { 223 if (hwconfig("gpio")) 224 config_board_mux(MUX_TYPE_GPIO); 225 226 return 0; 227 } 228 #endif 229 230 int board_init(void) 231 { 232 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 233 234 #ifdef CONFIG_SYS_FSL_SERDES 235 config_serdes_mux(); 236 #endif 237 238 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 239 enable_layerscape_ns_access(); 240 #endif 241 242 if (adjust_vdd(0)) 243 printf("Warning: Adjusting core voltage failed.\n"); 244 245 return 0; 246 } 247 248 #ifdef CONFIG_OF_BOARD_SETUP 249 int ft_board_setup(void *blob, bd_t *bd) 250 { 251 u64 base[CONFIG_NR_DRAM_BANKS]; 252 u64 size[CONFIG_NR_DRAM_BANKS]; 253 u8 reg; 254 255 /* fixup DT for the two DDR banks */ 256 base[0] = gd->bd->bi_dram[0].start; 257 size[0] = gd->bd->bi_dram[0].size; 258 base[1] = gd->bd->bi_dram[1].start; 259 size[1] = gd->bd->bi_dram[1].size; 260 261 fdt_fixup_memory_banks(blob, base, size, 2); 262 ft_cpu_setup(blob, bd); 263 264 #ifdef CONFIG_SYS_DPAA_FMAN 265 fdt_fixup_fman_ethernet(blob); 266 fdt_fixup_board_enet(blob); 267 #endif 268 269 reg = QIXIS_READ(brdcfg[0]); 270 reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 271 272 /* Disable IFC if QSPI is enabled */ 273 if (reg == 0xF) 274 do_fixup_by_compat(blob, "fsl,ifc", 275 "status", "disabled", 8 + 1, 1); 276 277 return 0; 278 } 279 #endif 280 281 u8 flash_read8(void *addr) 282 { 283 return __raw_readb(addr + 1); 284 } 285 286 void flash_write16(u16 val, void *addr) 287 { 288 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 289 290 __raw_writew(shftval, addr); 291 } 292 293 u16 flash_read16(void *addr) 294 { 295 u16 val = __raw_readw(addr); 296 297 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 298 } 299