1 /*
2  * Copyright 2016 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <i2c.h>
9 #include <fdt_support.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/fdt.h>
14 #include <asm/arch/soc.h>
15 #include <ahci.h>
16 #include <hwconfig.h>
17 #include <mmc.h>
18 #include <scsi.h>
19 #include <fm_eth.h>
20 #include <fsl_csu.h>
21 #include <fsl_esdhc.h>
22 #include <fsl_ifc.h>
23 #include <spl.h>
24 
25 #include "../common/vid.h"
26 #include "../common/qixis.h"
27 #include "ls1046aqds_qixis.h"
28 
29 DECLARE_GLOBAL_DATA_PTR;
30 
31 enum {
32 	MUX_TYPE_GPIO,
33 };
34 
35 int checkboard(void)
36 {
37 	char buf[64];
38 #ifndef CONFIG_SD_BOOT
39 	u8 sw;
40 #endif
41 
42 	puts("Board: LS1046AQDS, boot from ");
43 
44 #ifdef CONFIG_SD_BOOT
45 	puts("SD\n");
46 #else
47 	sw = QIXIS_READ(brdcfg[0]);
48 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
49 
50 	if (sw < 0x8)
51 		printf("vBank: %d\n", sw);
52 	else if (sw == 0x8)
53 		puts("PromJet\n");
54 	else if (sw == 0x9)
55 		puts("NAND\n");
56 	else if (sw == 0xF)
57 		printf("QSPI\n");
58 	else
59 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
60 #endif
61 
62 	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
63 	       QIXIS_READ(id), QIXIS_READ(arch));
64 
65 	printf("FPGA:  v%d (%s), build %d\n",
66 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
67 	       (int)qixis_read_minor());
68 
69 	return 0;
70 }
71 
72 bool if_board_diff_clk(void)
73 {
74 	u8 diff_conf = QIXIS_READ(brdcfg[11]);
75 
76 	return diff_conf & 0x40;
77 }
78 
79 unsigned long get_board_sys_clk(void)
80 {
81 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
82 
83 	switch (sysclk_conf & 0x0f) {
84 	case QIXIS_SYSCLK_64:
85 		return 64000000;
86 	case QIXIS_SYSCLK_83:
87 		return 83333333;
88 	case QIXIS_SYSCLK_100:
89 		return 100000000;
90 	case QIXIS_SYSCLK_125:
91 		return 125000000;
92 	case QIXIS_SYSCLK_133:
93 		return 133333333;
94 	case QIXIS_SYSCLK_150:
95 		return 150000000;
96 	case QIXIS_SYSCLK_160:
97 		return 160000000;
98 	case QIXIS_SYSCLK_166:
99 		return 166666666;
100 	}
101 
102 	return 66666666;
103 }
104 
105 unsigned long get_board_ddr_clk(void)
106 {
107 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
108 
109 	if (if_board_diff_clk())
110 		return get_board_sys_clk();
111 	switch ((ddrclk_conf & 0x30) >> 4) {
112 	case QIXIS_DDRCLK_100:
113 		return 100000000;
114 	case QIXIS_DDRCLK_125:
115 		return 125000000;
116 	case QIXIS_DDRCLK_133:
117 		return 133333333;
118 	}
119 
120 	return 66666666;
121 }
122 
123 #ifdef CONFIG_LPUART
124 u32 get_lpuart_clk(void)
125 {
126 	return gd->bus_clk;
127 }
128 #endif
129 
130 int select_i2c_ch_pca9547(u8 ch)
131 {
132 	int ret;
133 
134 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
135 	if (ret) {
136 		puts("PCA: failed to select proper channel\n");
137 		return ret;
138 	}
139 
140 	return 0;
141 }
142 
143 int dram_init(void)
144 {
145 	/*
146 	 * When resuming from deep sleep, the I2C channel may not be
147 	 * in the default channel. So, switch to the default channel
148 	 * before accessing DDR SPD.
149 	 */
150 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
151 	gd->ram_size = initdram(0);
152 
153 	return 0;
154 }
155 
156 int i2c_multiplexer_select_vid_channel(u8 channel)
157 {
158 	return select_i2c_ch_pca9547(channel);
159 }
160 
161 int board_early_init_f(void)
162 {
163 #ifdef CONFIG_HAS_FSL_XHCI_USB
164 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
165 	u32 usb_pwrfault;
166 #endif
167 #ifdef CONFIG_LPUART
168 	u8 uart;
169 #endif
170 
171 #ifdef CONFIG_SYS_I2C_EARLY_INIT
172 	i2c_early_init_f();
173 #endif
174 	fsl_lsch2_early_init_f();
175 
176 #ifdef CONFIG_HAS_FSL_XHCI_USB
177 	out_be32(&scfg->rcwpmuxcr0, 0x3333);
178 	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
179 	usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
180 			SCFG_USBPWRFAULT_USB3_SHIFT) |
181 			(SCFG_USBPWRFAULT_DEDICATED <<
182 			SCFG_USBPWRFAULT_USB2_SHIFT) |
183 			(SCFG_USBPWRFAULT_SHARED <<
184 			SCFG_USBPWRFAULT_USB1_SHIFT);
185 	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
186 #endif
187 
188 #ifdef CONFIG_LPUART
189 	/* We use lpuart0 as system console */
190 	uart = QIXIS_READ(brdcfg[14]);
191 	uart &= ~CFG_UART_MUX_MASK;
192 	uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
193 	QIXIS_WRITE(brdcfg[14], uart);
194 #endif
195 
196 	return 0;
197 }
198 
199 #ifdef CONFIG_FSL_DEEP_SLEEP
200 /* determine if it is a warm boot */
201 bool is_warm_boot(void)
202 {
203 #define DCFG_CCSR_CRSTSR_WDRFR	(1 << 3)
204 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
205 
206 	if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
207 		return 1;
208 
209 	return 0;
210 }
211 #endif
212 
213 int config_board_mux(int ctrl_type)
214 {
215 	u8 reg14;
216 
217 	reg14 = QIXIS_READ(brdcfg[14]);
218 
219 	switch (ctrl_type) {
220 	case MUX_TYPE_GPIO:
221 		reg14 = (reg14 & (~0x6)) | 0x2;
222 		break;
223 	default:
224 		puts("Unsupported mux interface type\n");
225 		return -1;
226 	}
227 
228 	QIXIS_WRITE(brdcfg[14], reg14);
229 
230 	return 0;
231 }
232 
233 int config_serdes_mux(void)
234 {
235 	return 0;
236 }
237 
238 #ifdef CONFIG_MISC_INIT_R
239 int misc_init_r(void)
240 {
241 	if (hwconfig("gpio"))
242 		config_board_mux(MUX_TYPE_GPIO);
243 
244 	return 0;
245 }
246 #endif
247 
248 int board_init(void)
249 {
250 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
251 
252 #ifdef CONFIG_SYS_FSL_SERDES
253 	config_serdes_mux();
254 #endif
255 
256 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
257 	enable_layerscape_ns_access();
258 #endif
259 
260 	if (adjust_vdd(0))
261 		printf("Warning: Adjusting core voltage failed.\n");
262 
263 	return 0;
264 }
265 
266 #ifdef CONFIG_OF_BOARD_SETUP
267 int ft_board_setup(void *blob, bd_t *bd)
268 {
269 	u64 base[CONFIG_NR_DRAM_BANKS];
270 	u64 size[CONFIG_NR_DRAM_BANKS];
271 	u8 reg;
272 
273 	/* fixup DT for the two DDR banks */
274 	base[0] = gd->bd->bi_dram[0].start;
275 	size[0] = gd->bd->bi_dram[0].size;
276 	base[1] = gd->bd->bi_dram[1].start;
277 	size[1] = gd->bd->bi_dram[1].size;
278 
279 	fdt_fixup_memory_banks(blob, base, size, 2);
280 	ft_cpu_setup(blob, bd);
281 
282 #ifdef CONFIG_SYS_DPAA_FMAN
283 	fdt_fixup_fman_ethernet(blob);
284 	fdt_fixup_board_enet(blob);
285 #endif
286 
287 	reg = QIXIS_READ(brdcfg[0]);
288 	reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
289 
290 	/* Disable IFC if QSPI is enabled */
291 	if (reg == 0xF)
292 		do_fixup_by_compat(blob, "fsl,ifc",
293 				   "status", "disabled", 8 + 1, 1);
294 
295 	return 0;
296 }
297 #endif
298 
299 u8 flash_read8(void *addr)
300 {
301 	return __raw_readb(addr + 1);
302 }
303 
304 void flash_write16(u16 val, void *addr)
305 {
306 	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
307 
308 	__raw_writew(shftval, addr);
309 }
310 
311 u16 flash_read16(void *addr)
312 {
313 	u16 val = __raw_readw(addr);
314 
315 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
316 }
317