1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <fdt_support.h> 10 #include <fsl_ddr_sdram.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/fsl_serdes.h> 14 #include <asm/arch/fdt.h> 15 #include <asm/arch/mmu.h> 16 #include <asm/arch/soc.h> 17 #include <ahci.h> 18 #include <hwconfig.h> 19 #include <mmc.h> 20 #include <scsi.h> 21 #include <fm_eth.h> 22 #include <fsl_csu.h> 23 #include <fsl_esdhc.h> 24 #include <fsl_ifc.h> 25 #include <spl.h> 26 27 #include "../common/vid.h" 28 #include "../common/qixis.h" 29 #include "ls1046aqds_qixis.h" 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 enum { 34 MUX_TYPE_GPIO, 35 }; 36 37 int checkboard(void) 38 { 39 char buf[64]; 40 #ifndef CONFIG_SD_BOOT 41 u8 sw; 42 #endif 43 44 puts("Board: LS1046AQDS, boot from "); 45 46 #ifdef CONFIG_SD_BOOT 47 puts("SD\n"); 48 #else 49 sw = QIXIS_READ(brdcfg[0]); 50 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 51 52 if (sw < 0x8) 53 printf("vBank: %d\n", sw); 54 else if (sw == 0x8) 55 puts("PromJet\n"); 56 else if (sw == 0x9) 57 puts("NAND\n"); 58 else if (sw == 0xF) 59 printf("QSPI\n"); 60 else 61 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 62 #endif 63 64 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", 65 QIXIS_READ(id), QIXIS_READ(arch)); 66 67 printf("FPGA: v%d (%s), build %d\n", 68 (int)QIXIS_READ(scver), qixis_read_tag(buf), 69 (int)qixis_read_minor()); 70 71 return 0; 72 } 73 74 bool if_board_diff_clk(void) 75 { 76 u8 diff_conf = QIXIS_READ(brdcfg[11]); 77 78 return diff_conf & 0x40; 79 } 80 81 unsigned long get_board_sys_clk(void) 82 { 83 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 84 85 switch (sysclk_conf & 0x0f) { 86 case QIXIS_SYSCLK_64: 87 return 64000000; 88 case QIXIS_SYSCLK_83: 89 return 83333333; 90 case QIXIS_SYSCLK_100: 91 return 100000000; 92 case QIXIS_SYSCLK_125: 93 return 125000000; 94 case QIXIS_SYSCLK_133: 95 return 133333333; 96 case QIXIS_SYSCLK_150: 97 return 150000000; 98 case QIXIS_SYSCLK_160: 99 return 160000000; 100 case QIXIS_SYSCLK_166: 101 return 166666666; 102 } 103 104 return 66666666; 105 } 106 107 unsigned long get_board_ddr_clk(void) 108 { 109 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 110 111 if (if_board_diff_clk()) 112 return get_board_sys_clk(); 113 switch ((ddrclk_conf & 0x30) >> 4) { 114 case QIXIS_DDRCLK_100: 115 return 100000000; 116 case QIXIS_DDRCLK_125: 117 return 125000000; 118 case QIXIS_DDRCLK_133: 119 return 133333333; 120 } 121 122 return 66666666; 123 } 124 125 #ifdef CONFIG_LPUART 126 u32 get_lpuart_clk(void) 127 { 128 return gd->bus_clk; 129 } 130 #endif 131 132 int select_i2c_ch_pca9547(u8 ch) 133 { 134 int ret; 135 136 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 137 if (ret) { 138 puts("PCA: failed to select proper channel\n"); 139 return ret; 140 } 141 142 return 0; 143 } 144 145 int dram_init(void) 146 { 147 /* 148 * When resuming from deep sleep, the I2C channel may not be 149 * in the default channel. So, switch to the default channel 150 * before accessing DDR SPD. 151 */ 152 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 153 fsl_initdram(); 154 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 155 /* This will break-before-make MMU for DDR */ 156 update_early_mmu_table(); 157 #endif 158 159 return 0; 160 } 161 162 int i2c_multiplexer_select_vid_channel(u8 channel) 163 { 164 return select_i2c_ch_pca9547(channel); 165 } 166 167 int board_early_init_f(void) 168 { 169 #ifdef CONFIG_HAS_FSL_XHCI_USB 170 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 171 u32 usb_pwrfault; 172 #endif 173 #ifdef CONFIG_LPUART 174 u8 uart; 175 #endif 176 177 #ifdef CONFIG_SYS_I2C_EARLY_INIT 178 i2c_early_init_f(); 179 #endif 180 fsl_lsch2_early_init_f(); 181 182 #ifdef CONFIG_HAS_FSL_XHCI_USB 183 out_be32(&scfg->rcwpmuxcr0, 0x3333); 184 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); 185 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << 186 SCFG_USBPWRFAULT_USB3_SHIFT) | 187 (SCFG_USBPWRFAULT_DEDICATED << 188 SCFG_USBPWRFAULT_USB2_SHIFT) | 189 (SCFG_USBPWRFAULT_SHARED << 190 SCFG_USBPWRFAULT_USB1_SHIFT); 191 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); 192 #endif 193 194 #ifdef CONFIG_LPUART 195 /* We use lpuart0 as system console */ 196 uart = QIXIS_READ(brdcfg[14]); 197 uart &= ~CFG_UART_MUX_MASK; 198 uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; 199 QIXIS_WRITE(brdcfg[14], uart); 200 #endif 201 202 return 0; 203 } 204 205 #ifdef CONFIG_FSL_DEEP_SLEEP 206 /* determine if it is a warm boot */ 207 bool is_warm_boot(void) 208 { 209 #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) 210 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 211 212 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) 213 return 1; 214 215 return 0; 216 } 217 #endif 218 219 int config_board_mux(int ctrl_type) 220 { 221 u8 reg14; 222 223 reg14 = QIXIS_READ(brdcfg[14]); 224 225 switch (ctrl_type) { 226 case MUX_TYPE_GPIO: 227 reg14 = (reg14 & (~0x6)) | 0x2; 228 break; 229 default: 230 puts("Unsupported mux interface type\n"); 231 return -1; 232 } 233 234 QIXIS_WRITE(brdcfg[14], reg14); 235 236 return 0; 237 } 238 239 int config_serdes_mux(void) 240 { 241 return 0; 242 } 243 244 #ifdef CONFIG_MISC_INIT_R 245 int misc_init_r(void) 246 { 247 if (hwconfig("gpio")) 248 config_board_mux(MUX_TYPE_GPIO); 249 250 return 0; 251 } 252 #endif 253 254 int board_init(void) 255 { 256 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 257 258 #ifdef CONFIG_SYS_FSL_SERDES 259 config_serdes_mux(); 260 #endif 261 262 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 263 enable_layerscape_ns_access(); 264 #endif 265 266 if (adjust_vdd(0)) 267 printf("Warning: Adjusting core voltage failed.\n"); 268 269 return 0; 270 } 271 272 #ifdef CONFIG_OF_BOARD_SETUP 273 int ft_board_setup(void *blob, bd_t *bd) 274 { 275 u64 base[CONFIG_NR_DRAM_BANKS]; 276 u64 size[CONFIG_NR_DRAM_BANKS]; 277 u8 reg; 278 279 /* fixup DT for the two DDR banks */ 280 base[0] = gd->bd->bi_dram[0].start; 281 size[0] = gd->bd->bi_dram[0].size; 282 base[1] = gd->bd->bi_dram[1].start; 283 size[1] = gd->bd->bi_dram[1].size; 284 285 fdt_fixup_memory_banks(blob, base, size, 2); 286 ft_cpu_setup(blob, bd); 287 288 #ifdef CONFIG_SYS_DPAA_FMAN 289 fdt_fixup_fman_ethernet(blob); 290 fdt_fixup_board_enet(blob); 291 #endif 292 293 reg = QIXIS_READ(brdcfg[0]); 294 reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 295 296 /* Disable IFC if QSPI is enabled */ 297 if (reg == 0xF) 298 do_fixup_by_compat(blob, "fsl,ifc", 299 "status", "disabled", 8 + 1, 1); 300 301 return 0; 302 } 303 #endif 304 305 u8 flash_read8(void *addr) 306 { 307 return __raw_readb(addr + 1); 308 } 309 310 void flash_write16(u16 val, void *addr) 311 { 312 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 313 314 __raw_writew(shftval, addr); 315 } 316 317 u16 flash_read16(void *addr) 318 { 319 u16 val = __raw_readw(addr); 320 321 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 322 } 323