1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2016 Freescale Semiconductor, Inc.
4  * Copyright 2018 NXP
5  */
6 
7 #include <common.h>
8 #include <asm/io.h>
9 #include <netdev.h>
10 #include <fdt_support.h>
11 #include <fm_eth.h>
12 #include <fsl_mdio.h>
13 #include <fsl_dtsec.h>
14 #include <malloc.h>
15 #include <asm/arch/fsl_serdes.h>
16 
17 #include "../common/qixis.h"
18 #include "../common/fman.h"
19 #include "ls1046aqds_qixis.h"
20 
21 #define EMI_NONE	0xFF
22 #define EMI1_RGMII1	0
23 #define EMI1_RGMII2	1
24 #define EMI1_SLOT1	2
25 #define EMI1_SLOT2	3
26 #define EMI1_SLOT4	4
27 
28 static int mdio_mux[NUM_FM_PORTS];
29 
30 static const char * const mdio_names[] = {
31 	"LS1046AQDS_MDIO_RGMII1",
32 	"LS1046AQDS_MDIO_RGMII2",
33 	"LS1046AQDS_MDIO_SLOT1",
34 	"LS1046AQDS_MDIO_SLOT2",
35 	"LS1046AQDS_MDIO_SLOT4",
36 	"NULL",
37 };
38 
39 /* Map SerDes 1 & 2 lanes to default slot. */
40 static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0};
41 
ls1046aqds_mdio_name_for_muxval(u8 muxval)42 static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval)
43 {
44 	return mdio_names[muxval];
45 }
46 
mii_dev_for_muxval(u8 muxval)47 struct mii_dev *mii_dev_for_muxval(u8 muxval)
48 {
49 	struct mii_dev *bus;
50 	const char *name;
51 
52 	if (muxval > EMI1_SLOT4)
53 		return NULL;
54 
55 	name = ls1046aqds_mdio_name_for_muxval(muxval);
56 
57 	if (!name) {
58 		printf("No bus for muxval %x\n", muxval);
59 		return NULL;
60 	}
61 
62 	bus = miiphy_get_dev_by_name(name);
63 
64 	if (!bus) {
65 		printf("No bus by name %s\n", name);
66 		return NULL;
67 	}
68 
69 	return bus;
70 }
71 
72 struct ls1046aqds_mdio {
73 	u8 muxval;
74 	struct mii_dev *realbus;
75 };
76 
ls1046aqds_mux_mdio(u8 muxval)77 static void ls1046aqds_mux_mdio(u8 muxval)
78 {
79 	u8 brdcfg4;
80 
81 	if (muxval < 7) {
82 		brdcfg4 = QIXIS_READ(brdcfg[4]);
83 		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
84 		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
85 		QIXIS_WRITE(brdcfg[4], brdcfg4);
86 	}
87 }
88 
ls1046aqds_mdio_read(struct mii_dev * bus,int addr,int devad,int regnum)89 static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
90 			      int regnum)
91 {
92 	struct ls1046aqds_mdio *priv = bus->priv;
93 
94 	ls1046aqds_mux_mdio(priv->muxval);
95 
96 	return priv->realbus->read(priv->realbus, addr, devad, regnum);
97 }
98 
ls1046aqds_mdio_write(struct mii_dev * bus,int addr,int devad,int regnum,u16 value)99 static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
100 			       int regnum, u16 value)
101 {
102 	struct ls1046aqds_mdio *priv = bus->priv;
103 
104 	ls1046aqds_mux_mdio(priv->muxval);
105 
106 	return priv->realbus->write(priv->realbus, addr, devad,
107 				    regnum, value);
108 }
109 
ls1046aqds_mdio_reset(struct mii_dev * bus)110 static int ls1046aqds_mdio_reset(struct mii_dev *bus)
111 {
112 	struct ls1046aqds_mdio *priv = bus->priv;
113 
114 	return priv->realbus->reset(priv->realbus);
115 }
116 
ls1046aqds_mdio_init(char * realbusname,u8 muxval)117 static int ls1046aqds_mdio_init(char *realbusname, u8 muxval)
118 {
119 	struct ls1046aqds_mdio *pmdio;
120 	struct mii_dev *bus = mdio_alloc();
121 
122 	if (!bus) {
123 		printf("Failed to allocate ls1046aqds MDIO bus\n");
124 		return -1;
125 	}
126 
127 	pmdio = malloc(sizeof(*pmdio));
128 	if (!pmdio) {
129 		printf("Failed to allocate ls1046aqds private data\n");
130 		free(bus);
131 		return -1;
132 	}
133 
134 	bus->read = ls1046aqds_mdio_read;
135 	bus->write = ls1046aqds_mdio_write;
136 	bus->reset = ls1046aqds_mdio_reset;
137 	sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval));
138 
139 	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
140 
141 	if (!pmdio->realbus) {
142 		printf("No bus with name %s\n", realbusname);
143 		free(bus);
144 		free(pmdio);
145 		return -1;
146 	}
147 
148 	pmdio->muxval = muxval;
149 	bus->priv = pmdio;
150 	return mdio_register(bus);
151 }
152 
board_ft_fman_fixup_port(void * fdt,char * compat,phys_addr_t addr,enum fm_port port,int offset)153 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
154 			      enum fm_port port, int offset)
155 {
156 	struct fixed_link f_link;
157 	const u32 *handle;
158 	const char *prop = NULL;
159 	int off;
160 
161 	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
162 		switch (port) {
163 		case FM1_DTSEC9:
164 			fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p1");
165 			break;
166 		case FM1_DTSEC10:
167 			fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p2");
168 			break;
169 		case FM1_DTSEC5:
170 			fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p3");
171 			break;
172 		case FM1_DTSEC6:
173 			fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p4");
174 			break;
175 		case FM1_DTSEC2:
176 			fdt_set_phy_handle(fdt, compat, addr, "sgmii_s4_p1");
177 			break;
178 		default:
179 			break;
180 		}
181 	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
182 		/* 2.5G SGMII interface */
183 		f_link.phy_id = cpu_to_fdt32(port);
184 		f_link.duplex = cpu_to_fdt32(1);
185 		f_link.link_speed = cpu_to_fdt32(1000);
186 		f_link.pause = 0;
187 		f_link.asym_pause = 0;
188 		/* no PHY for 2.5G SGMII on QDS */
189 		fdt_delprop(fdt, offset, "phy-handle");
190 		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
191 		fdt_setprop_string(fdt, offset, "phy-connection-type",
192 				   "sgmii-2500");
193 	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
194 		switch (port) {
195 		case FM1_DTSEC1:
196 			fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p4");
197 			break;
198 		case FM1_DTSEC5:
199 			fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p2");
200 			break;
201 		case FM1_DTSEC6:
202 			fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p1");
203 			break;
204 		case FM1_DTSEC10:
205 			fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p3");
206 			break;
207 		default:
208 			break;
209 		}
210 		fdt_delprop(fdt, offset, "phy-connection-type");
211 		fdt_setprop_string(fdt, offset, "phy-connection-type",
212 				   "qsgmii");
213 	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
214 		   (port == FM1_10GEC1 || port == FM1_10GEC2)) {
215 		handle = fdt_getprop(fdt, offset, "phy-handle", NULL);
216 		prop = NULL;
217 		if (handle) {
218 			off = fdt_node_offset_by_phandle(fdt,
219 							 fdt32_to_cpu(*handle));
220 			prop = fdt_getprop(fdt, off, "backplane-mode", NULL);
221 		}
222 		if (!prop || strcmp(prop, "10gbase-kr")) {
223 			/* XFI interface */
224 			f_link.phy_id = cpu_to_fdt32(port);
225 			f_link.duplex = cpu_to_fdt32(1);
226 			f_link.link_speed = cpu_to_fdt32(10000);
227 			f_link.pause = 0;
228 			f_link.asym_pause = 0;
229 			/* no PHY for XFI */
230 			fdt_delprop(fdt, offset, "phy-handle");
231 			fdt_setprop(fdt, offset, "fixed-link", &f_link,
232 				    sizeof(f_link));
233 			fdt_setprop_string(fdt, offset, "phy-connection-type",
234 					   "xgmii");
235 		}
236 	}
237 }
238 
fdt_fixup_board_enet(void * fdt)239 void fdt_fixup_board_enet(void *fdt)
240 {
241 	int i;
242 
243 	for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
244 		switch (fm_info_get_enet_if(i)) {
245 		case PHY_INTERFACE_MODE_SGMII:
246 		case PHY_INTERFACE_MODE_QSGMII:
247 			switch (mdio_mux[i]) {
248 			case EMI1_SLOT1:
249 				fdt_status_okay_by_alias(fdt, "emi1_slot1");
250 				break;
251 			case EMI1_SLOT2:
252 				fdt_status_okay_by_alias(fdt, "emi1_slot2");
253 				break;
254 			case EMI1_SLOT4:
255 				fdt_status_okay_by_alias(fdt, "emi1_slot4");
256 				break;
257 			default:
258 				break;
259 			}
260 			break;
261 		default:
262 			break;
263 		}
264 	}
265 }
266 
board_eth_init(bd_t * bis)267 int board_eth_init(bd_t *bis)
268 {
269 #ifdef CONFIG_FMAN_ENET
270 	int i, idx, lane, slot, interface;
271 	struct memac_mdio_info dtsec_mdio_info;
272 	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
273 	u32 srds_s1, srds_s2;
274 	u8 brdcfg12;
275 
276 	srds_s1 = in_be32(&gur->rcwsr[4]) &
277 			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
278 	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
279 
280 	srds_s2 = in_be32(&gur->rcwsr[4]) &
281 			FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
282 	srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
283 
284 	/* Initialize the mdio_mux array so we can recognize empty elements */
285 	for (i = 0; i < NUM_FM_PORTS; i++)
286 		mdio_mux[i] = EMI_NONE;
287 
288 	dtsec_mdio_info.regs =
289 		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
290 
291 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
292 
293 	/* Register the 1G MDIO bus */
294 	fm_memac_mdio_init(bis, &dtsec_mdio_info);
295 
296 	/* Register the muxing front-ends to the MDIO buses */
297 	ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
298 	ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
299 	ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
300 	ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
301 	ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
302 
303 	/* Set the two on-board RGMII PHY address */
304 	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
305 	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
306 
307 	switch (srds_s1) {
308 	case 0x3333:
309 		/* SGMII on slot 1, MAC 9 */
310 		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
311 	case 0x1333:
312 	case 0x2333:
313 		/* SGMII on slot 1, MAC 10 */
314 		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
315 	case 0x1133:
316 	case 0x2233:
317 		/* SGMII on slot 1, MAC 5/6 */
318 		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
319 		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
320 		break;
321 	case 0x1040:
322 	case 0x2040:
323 		/* QSGMII on lane B, MAC 6/5/10/1 */
324 		fm_info_set_phy_address(FM1_DTSEC6,
325 					QSGMII_CARD_PORT1_PHY_ADDR_S2);
326 		fm_info_set_phy_address(FM1_DTSEC5,
327 					QSGMII_CARD_PORT2_PHY_ADDR_S2);
328 		fm_info_set_phy_address(FM1_DTSEC10,
329 					QSGMII_CARD_PORT3_PHY_ADDR_S2);
330 		fm_info_set_phy_address(FM1_DTSEC1,
331 					QSGMII_CARD_PORT4_PHY_ADDR_S2);
332 		break;
333 	case 0x3363:
334 		/* SGMII on slot 1, MAC 9/10 */
335 		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
336 		fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
337 	case 0x1163:
338 	case 0x2263:
339 	case 0x2223:
340 		/* SGMII on slot 1, MAC 6 */
341 		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
342 		break;
343 	default:
344 		printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n",
345 		       srds_s1);
346 		break;
347 	}
348 
349 	if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06)
350 		/* SGMII on slot 4, MAC 2 */
351 		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
352 
353 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
354 		idx = i - FM1_DTSEC1;
355 		interface = fm_info_get_enet_if(i);
356 		switch (interface) {
357 		case PHY_INTERFACE_MODE_SGMII:
358 		case PHY_INTERFACE_MODE_QSGMII:
359 			if (interface == PHY_INTERFACE_MODE_SGMII) {
360 				if (i == FM1_DTSEC5) {
361 					/* route lane 2 to slot1 so to have
362 					 * one sgmii riser card supports
363 					 * MAC5 and MAC6.
364 					 */
365 					brdcfg12 = QIXIS_READ(brdcfg[12]);
366 					QIXIS_WRITE(brdcfg[12],
367 						    brdcfg12 | 0x80);
368 				}
369 				lane = serdes_get_first_lane(FSL_SRDS_1,
370 						SGMII_FM1_DTSEC1 + idx);
371 			} else {
372 				/* clear the bit 7 to route lane B on slot2. */
373 				brdcfg12 = QIXIS_READ(brdcfg[12]);
374 				QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f);
375 
376 				lane = serdes_get_first_lane(FSL_SRDS_1,
377 						QSGMII_FM1_A);
378 				lane_to_slot[lane] = 2;
379 			}
380 
381 			if (i == FM1_DTSEC2)
382 				lane = 5;
383 
384 			if (lane < 0)
385 				break;
386 
387 			slot = lane_to_slot[lane];
388 			debug("FM1@DTSEC%u expects SGMII in slot %u\n",
389 			      idx + 1, slot);
390 			if (QIXIS_READ(present2) & (1 << (slot - 1)))
391 				fm_disable_port(i);
392 
393 			switch (slot) {
394 			case 1:
395 				mdio_mux[i] = EMI1_SLOT1;
396 				fm_info_set_mdio(i, mii_dev_for_muxval(
397 						 mdio_mux[i]));
398 				break;
399 			case 2:
400 				mdio_mux[i] = EMI1_SLOT2;
401 				fm_info_set_mdio(i, mii_dev_for_muxval(
402 						 mdio_mux[i]));
403 				break;
404 			case 4:
405 				mdio_mux[i] = EMI1_SLOT4;
406 				fm_info_set_mdio(i, mii_dev_for_muxval(
407 						 mdio_mux[i]));
408 				break;
409 			default:
410 				break;
411 			}
412 			break;
413 		case PHY_INTERFACE_MODE_RGMII:
414 		case PHY_INTERFACE_MODE_RGMII_TXID:
415 			if (i == FM1_DTSEC3)
416 				mdio_mux[i] = EMI1_RGMII1;
417 			else if (i == FM1_DTSEC4)
418 				mdio_mux[i] = EMI1_RGMII2;
419 			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
420 			break;
421 		default:
422 			break;
423 		}
424 	}
425 
426 	cpu_eth_init(bis);
427 #endif /* CONFIG_FMAN_ENET */
428 
429 	return pci_eth_init(bis);
430 }
431