1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fsl_ddr_sdram.h> 9 #include <fsl_ddr_dimm_params.h> 10 #ifdef CONFIG_FSL_DEEP_SLEEP 11 #include <fsl_sleep.h> 12 #endif 13 #include <asm/arch/clock.h> 14 #include "ddr.h" 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 void fsl_ddr_board_options(memctl_options_t *popts, 19 dimm_params_t *pdimm, 20 unsigned int ctrl_num) 21 { 22 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 23 ulong ddr_freq; 24 25 if (ctrl_num > 3) { 26 printf("Not supported controller number %d\n", ctrl_num); 27 return; 28 } 29 if (!pdimm->n_ranks) 30 return; 31 32 pbsp = udimms[0]; 33 34 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr 35 * freqency and n_banks specified in board_specific_parameters table. 36 */ 37 ddr_freq = get_ddr_freq(0) / 1000000; 38 while (pbsp->datarate_mhz_high) { 39 if (pbsp->n_ranks == pdimm->n_ranks) { 40 if (ddr_freq <= pbsp->datarate_mhz_high) { 41 popts->clk_adjust = pbsp->clk_adjust; 42 popts->wrlvl_start = pbsp->wrlvl_start; 43 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 44 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 45 goto found; 46 } 47 pbsp_highest = pbsp; 48 } 49 pbsp++; 50 } 51 52 if (pbsp_highest) { 53 printf("Error: board specific timing not found for %lu MT/s\n", 54 ddr_freq); 55 printf("Trying to use the highest speed (%u) parameters\n", 56 pbsp_highest->datarate_mhz_high); 57 popts->clk_adjust = pbsp_highest->clk_adjust; 58 popts->wrlvl_start = pbsp_highest->wrlvl_start; 59 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 60 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 61 } else { 62 panic("DIMM is not supported by this board"); 63 } 64 found: 65 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", 66 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); 67 68 popts->data_bus_width = 0; /* 64b data bus */ 69 popts->otf_burst_chop_en = 0; 70 popts->burst_length = DDR_BL8; 71 popts->bstopre = 0; /* enable auto precharge */ 72 73 popts->half_strength_driver_enable = 0; 74 /* 75 * Write leveling override 76 */ 77 popts->wrlvl_override = 1; 78 popts->wrlvl_sample = 0xf; 79 80 /* 81 * Rtt and Rtt_WR override 82 */ 83 popts->rtt_override = 0; 84 85 /* Enable ZQ calibration */ 86 popts->zq_en = 1; 87 88 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); 89 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | 90 DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; 91 92 /* optimize cpo for erratum A-009942 */ 93 popts->cpo_sample = 0x70; 94 } 95 96 int fsl_initdram(void) 97 { 98 phys_size_t dram_size; 99 100 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) 101 gd->ram_size = fsl_ddr_sdram_size(); 102 103 return 0; 104 #else 105 puts("Initializing DDR....using SPD\n"); 106 107 dram_size = fsl_ddr_sdram(); 108 #endif 109 110 #ifdef CONFIG_FSL_DEEP_SLEEP 111 fsl_dp_ddr_restore(); 112 #endif 113 114 erratum_a008850_post(); 115 116 gd->ram_size = dram_size; 117 118 return 0; 119 } 120