1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/fsl_serdes.h> 12 #include <asm/arch/soc.h> 13 #include <fdt_support.h> 14 #include <hwconfig.h> 15 #include <ahci.h> 16 #include <mmc.h> 17 #include <scsi.h> 18 #include <fm_eth.h> 19 #include <fsl_esdhc.h> 20 #include <fsl_ifc.h> 21 #include <fsl_sec.h> 22 #include "cpld.h" 23 #ifdef CONFIG_U_QE 24 #include <fsl_qe.h> 25 #endif 26 #include <asm/arch/ppa.h> 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 int checkboard(void) 31 { 32 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; 33 #ifndef CONFIG_SD_BOOT 34 u8 cfg_rcw_src1, cfg_rcw_src2; 35 u16 cfg_rcw_src; 36 #endif 37 u8 sd1refclk_sel; 38 39 printf("Board: LS1043ARDB, boot from "); 40 41 #ifdef CONFIG_SD_BOOT 42 puts("SD\n"); 43 #else 44 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); 45 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); 46 cpld_rev_bit(&cfg_rcw_src1); 47 cfg_rcw_src = cfg_rcw_src1; 48 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; 49 50 if (cfg_rcw_src == 0x25) 51 printf("vBank %d\n", CPLD_READ(vbank)); 52 else if (cfg_rcw_src == 0x106) 53 puts("NAND\n"); 54 else 55 printf("Invalid setting of SW4\n"); 56 #endif 57 58 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), 59 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); 60 61 puts("SERDES Reference Clocks:\n"); 62 sd1refclk_sel = CPLD_READ(sd1refclk_sel); 63 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); 64 65 return 0; 66 } 67 68 int board_early_init_f(void) 69 { 70 fsl_lsch2_early_init_f(); 71 72 return 0; 73 } 74 75 int board_init(void) 76 { 77 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 78 79 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 80 erratum_a010315(); 81 #endif 82 83 #ifdef CONFIG_FSL_IFC 84 init_final_memctl_regs(); 85 #endif 86 87 #ifdef CONFIG_SECURE_BOOT 88 /* In case of Secure Boot, the IBR configures the SMMU 89 * to allow only Secure transactions. 90 * SMMU must be reset in bypass mode. 91 * Set the ClientPD bit and Clear the USFCFG Bit 92 */ 93 u32 val; 94 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 95 out_le32(SMMU_SCR0, val); 96 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 97 out_le32(SMMU_NSCR0, val); 98 #endif 99 100 #ifdef CONFIG_FSL_CAAM 101 sec_init(); 102 #endif 103 104 #ifdef CONFIG_FSL_LS_PPA 105 ppa_init(); 106 #endif 107 108 #ifdef CONFIG_U_QE 109 u_qe_init(); 110 #endif 111 /* invert AQR105 IRQ pins polarity */ 112 out_be32(&scfg->intpcr, AQR105_IRQ_MASK); 113 114 return 0; 115 } 116 117 int config_board_mux(void) 118 { 119 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 120 u32 usb_pwrfault; 121 122 if (hwconfig("qe-hdlc")) { 123 out_be32(&scfg->rcwpmuxcr0, 124 (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600); 125 printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n", 126 in_be32(&scfg->rcwpmuxcr0)); 127 } else { 128 #ifdef CONFIG_HAS_FSL_XHCI_USB 129 out_be32(&scfg->rcwpmuxcr0, 0x3333); 130 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); 131 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << 132 SCFG_USBPWRFAULT_USB3_SHIFT) | 133 (SCFG_USBPWRFAULT_DEDICATED << 134 SCFG_USBPWRFAULT_USB2_SHIFT) | 135 (SCFG_USBPWRFAULT_SHARED << 136 SCFG_USBPWRFAULT_USB1_SHIFT); 137 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); 138 #endif 139 } 140 return 0; 141 } 142 143 #if defined(CONFIG_MISC_INIT_R) 144 int misc_init_r(void) 145 { 146 config_board_mux(); 147 return 0; 148 } 149 #endif 150 151 void fdt_del_qe(void *blob) 152 { 153 int nodeoff = 0; 154 155 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 156 "fsl,qe")) >= 0) { 157 fdt_del_node(blob, nodeoff); 158 } 159 } 160 161 int ft_board_setup(void *blob, bd_t *bd) 162 { 163 u64 base[CONFIG_NR_DRAM_BANKS]; 164 u64 size[CONFIG_NR_DRAM_BANKS]; 165 166 /* fixup DT for the two DDR banks */ 167 base[0] = gd->bd->bi_dram[0].start; 168 size[0] = gd->bd->bi_dram[0].size; 169 base[1] = gd->bd->bi_dram[1].start; 170 size[1] = gd->bd->bi_dram[1].size; 171 172 fdt_fixup_memory_banks(blob, base, size, 2); 173 ft_cpu_setup(blob, bd); 174 175 #ifdef CONFIG_SYS_DPAA_FMAN 176 fdt_fixup_fman_ethernet(blob); 177 #endif 178 179 /* 180 * qe-hdlc and usb multi-use the pins, 181 * when set hwconfig to qe-hdlc, delete usb node. 182 */ 183 if (hwconfig("qe-hdlc")) 184 #ifdef CONFIG_HAS_FSL_XHCI_USB 185 fdt_del_node_and_alias(blob, "usb1"); 186 #endif 187 /* 188 * qe just support qe-uart and qe-hdlc, 189 * if qe-uart and qe-hdlc are not set in hwconfig, 190 * delete qe node. 191 */ 192 if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc")) 193 fdt_del_qe(blob); 194 195 return 0; 196 } 197 198 u8 flash_read8(void *addr) 199 { 200 return __raw_readb(addr + 1); 201 } 202 203 void flash_write16(u16 val, void *addr) 204 { 205 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 206 207 __raw_writew(shftval, addr); 208 } 209 210 u16 flash_read16(void *addr) 211 { 212 u16 val = __raw_readw(addr); 213 214 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 215 } 216