1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/fsl_serdes.h> 12 #include <asm/arch/soc.h> 13 #include <fdt_support.h> 14 #include <hwconfig.h> 15 #include <ahci.h> 16 #include <mmc.h> 17 #include <scsi.h> 18 #include <fm_eth.h> 19 #include <fsl_csu.h> 20 #include <fsl_esdhc.h> 21 #include <fsl_ifc.h> 22 #include <fsl_sec.h> 23 #include "cpld.h" 24 #ifdef CONFIG_U_QE 25 #include <fsl_qe.h> 26 #endif 27 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 int checkboard(void) 32 { 33 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; 34 #ifndef CONFIG_SD_BOOT 35 u8 cfg_rcw_src1, cfg_rcw_src2; 36 u16 cfg_rcw_src; 37 #endif 38 u8 sd1refclk_sel; 39 40 printf("Board: LS1043ARDB, boot from "); 41 42 #ifdef CONFIG_SD_BOOT 43 puts("SD\n"); 44 #else 45 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); 46 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); 47 cpld_rev_bit(&cfg_rcw_src1); 48 cfg_rcw_src = cfg_rcw_src1; 49 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; 50 51 if (cfg_rcw_src == 0x25) 52 printf("vBank %d\n", CPLD_READ(vbank)); 53 else if (cfg_rcw_src == 0x106) 54 puts("NAND\n"); 55 else 56 printf("Invalid setting of SW4\n"); 57 #endif 58 59 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), 60 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); 61 62 puts("SERDES Reference Clocks:\n"); 63 sd1refclk_sel = CPLD_READ(sd1refclk_sel); 64 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); 65 66 return 0; 67 } 68 69 int dram_init(void) 70 { 71 gd->ram_size = initdram(0); 72 73 return 0; 74 } 75 76 int board_early_init_f(void) 77 { 78 fsl_lsch2_early_init_f(); 79 80 return 0; 81 } 82 83 int board_init(void) 84 { 85 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 86 87 #ifdef CONFIG_FSL_IFC 88 init_final_memctl_regs(); 89 #endif 90 91 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 92 enable_layerscape_ns_access(); 93 #endif 94 95 #ifdef CONFIG_U_QE 96 u_qe_init(); 97 #endif 98 /* invert AQR105 IRQ pins polarity */ 99 out_be32(&scfg->intpcr, AQR105_IRQ_MASK); 100 101 return 0; 102 } 103 104 int config_board_mux(void) 105 { 106 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 107 u32 usb_pwrfault; 108 109 if (hwconfig("qe-hdlc")) { 110 out_be32(&scfg->rcwpmuxcr0, 111 (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600); 112 printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n", 113 in_be32(&scfg->rcwpmuxcr0)); 114 } else { 115 #ifdef CONFIG_HAS_FSL_XHCI_USB 116 out_be32(&scfg->rcwpmuxcr0, 0x3333); 117 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); 118 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << 119 SCFG_USBPWRFAULT_USB3_SHIFT) | 120 (SCFG_USBPWRFAULT_DEDICATED << 121 SCFG_USBPWRFAULT_USB2_SHIFT) | 122 (SCFG_USBPWRFAULT_SHARED << 123 SCFG_USBPWRFAULT_USB1_SHIFT); 124 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); 125 #endif 126 } 127 return 0; 128 } 129 130 #if defined(CONFIG_MISC_INIT_R) 131 int misc_init_r(void) 132 { 133 config_board_mux(); 134 #ifdef CONFIG_SECURE_BOOT 135 /* In case of Secure Boot, the IBR configures the SMMU 136 * to allow only Secure transactions. 137 * SMMU must be reset in bypass mode. 138 * Set the ClientPD bit and Clear the USFCFG Bit 139 */ 140 u32 val; 141 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 142 out_le32(SMMU_SCR0, val); 143 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 144 out_le32(SMMU_NSCR0, val); 145 #endif 146 #ifdef CONFIG_FSL_CAAM 147 return sec_init(); 148 #endif 149 return 0; 150 } 151 #endif 152 153 void fdt_del_qe(void *blob) 154 { 155 int nodeoff = 0; 156 157 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 158 "fsl,qe")) >= 0) { 159 fdt_del_node(blob, nodeoff); 160 } 161 } 162 163 int ft_board_setup(void *blob, bd_t *bd) 164 { 165 u64 base[CONFIG_NR_DRAM_BANKS]; 166 u64 size[CONFIG_NR_DRAM_BANKS]; 167 168 /* fixup DT for the two DDR banks */ 169 base[0] = gd->bd->bi_dram[0].start; 170 size[0] = gd->bd->bi_dram[0].size; 171 base[1] = gd->bd->bi_dram[1].start; 172 size[1] = gd->bd->bi_dram[1].size; 173 174 fdt_fixup_memory_banks(blob, base, size, 2); 175 ft_cpu_setup(blob, bd); 176 177 #ifdef CONFIG_SYS_DPAA_FMAN 178 fdt_fixup_fman_ethernet(blob); 179 #endif 180 181 /* 182 * qe-hdlc and usb multi-use the pins, 183 * when set hwconfig to qe-hdlc, delete usb node. 184 */ 185 if (hwconfig("qe-hdlc")) 186 #ifdef CONFIG_HAS_FSL_XHCI_USB 187 fdt_del_node_and_alias(blob, "usb1"); 188 #endif 189 /* 190 * qe just support qe-uart and qe-hdlc, 191 * if qe-uart and qe-hdlc are not set in hwconfig, 192 * delete qe node. 193 */ 194 if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc")) 195 fdt_del_qe(blob); 196 197 return 0; 198 } 199 200 u8 flash_read8(void *addr) 201 { 202 return __raw_readb(addr + 1); 203 } 204 205 void flash_write16(u16 val, void *addr) 206 { 207 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 208 209 __raw_writew(shftval, addr); 210 } 211 212 u16 flash_read16(void *addr) 213 { 214 u16 val = __raw_readw(addr); 215 216 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 217 } 218