1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2015 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <i2c.h> 8 #include <asm/io.h> 9 #include <asm/arch/clock.h> 10 #include <asm/arch/fsl_serdes.h> 11 #include <asm/arch/soc.h> 12 #include <fdt_support.h> 13 #include <hwconfig.h> 14 #include <ahci.h> 15 #include <mmc.h> 16 #include <scsi.h> 17 #include <fm_eth.h> 18 #include <fsl_esdhc.h> 19 #include <fsl_ifc.h> 20 #include <fsl_sec.h> 21 #include "cpld.h" 22 #ifdef CONFIG_U_QE 23 #include <fsl_qe.h> 24 #endif 25 #include <asm/arch/ppa.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 int board_early_init_f(void) 30 { 31 fsl_lsch2_early_init_f(); 32 33 return 0; 34 } 35 36 #ifndef CONFIG_SPL_BUILD 37 38 int checkboard(void) 39 { 40 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; 41 #ifndef CONFIG_SD_BOOT 42 u8 cfg_rcw_src1, cfg_rcw_src2; 43 u16 cfg_rcw_src; 44 #endif 45 u8 sd1refclk_sel; 46 47 printf("Board: LS1043ARDB, boot from "); 48 49 #ifdef CONFIG_SD_BOOT 50 puts("SD\n"); 51 #else 52 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); 53 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); 54 cpld_rev_bit(&cfg_rcw_src1); 55 cfg_rcw_src = cfg_rcw_src1; 56 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; 57 58 if (cfg_rcw_src == 0x25) 59 printf("vBank %d\n", CPLD_READ(vbank)); 60 else if (cfg_rcw_src == 0x106) 61 puts("NAND\n"); 62 else 63 printf("Invalid setting of SW4\n"); 64 #endif 65 66 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), 67 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); 68 69 puts("SERDES Reference Clocks:\n"); 70 sd1refclk_sel = CPLD_READ(sd1refclk_sel); 71 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); 72 73 return 0; 74 } 75 76 int board_init(void) 77 { 78 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 79 80 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 81 erratum_a010315(); 82 #endif 83 84 #ifdef CONFIG_FSL_IFC 85 init_final_memctl_regs(); 86 #endif 87 88 #ifdef CONFIG_SECURE_BOOT 89 /* In case of Secure Boot, the IBR configures the SMMU 90 * to allow only Secure transactions. 91 * SMMU must be reset in bypass mode. 92 * Set the ClientPD bit and Clear the USFCFG Bit 93 */ 94 u32 val; 95 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 96 out_le32(SMMU_SCR0, val); 97 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 98 out_le32(SMMU_NSCR0, val); 99 #endif 100 101 #ifdef CONFIG_FSL_CAAM 102 sec_init(); 103 #endif 104 105 #ifdef CONFIG_FSL_LS_PPA 106 ppa_init(); 107 #endif 108 109 #ifdef CONFIG_U_QE 110 u_qe_init(); 111 #endif 112 /* invert AQR105 IRQ pins polarity */ 113 out_be32(&scfg->intpcr, AQR105_IRQ_MASK); 114 115 return 0; 116 } 117 118 int config_board_mux(void) 119 { 120 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 121 u32 usb_pwrfault; 122 123 if (hwconfig("qe-hdlc")) { 124 out_be32(&scfg->rcwpmuxcr0, 125 (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600); 126 printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n", 127 in_be32(&scfg->rcwpmuxcr0)); 128 } else { 129 #ifdef CONFIG_HAS_FSL_XHCI_USB 130 out_be32(&scfg->rcwpmuxcr0, 0x3333); 131 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); 132 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << 133 SCFG_USBPWRFAULT_USB3_SHIFT) | 134 (SCFG_USBPWRFAULT_DEDICATED << 135 SCFG_USBPWRFAULT_USB2_SHIFT) | 136 (SCFG_USBPWRFAULT_SHARED << 137 SCFG_USBPWRFAULT_USB1_SHIFT); 138 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); 139 #endif 140 } 141 return 0; 142 } 143 144 #if defined(CONFIG_MISC_INIT_R) 145 int misc_init_r(void) 146 { 147 config_board_mux(); 148 return 0; 149 } 150 #endif 151 152 void fdt_del_qe(void *blob) 153 { 154 int nodeoff = 0; 155 156 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, 157 "fsl,qe")) >= 0) { 158 fdt_del_node(blob, nodeoff); 159 } 160 } 161 162 int ft_board_setup(void *blob, bd_t *bd) 163 { 164 u64 base[CONFIG_NR_DRAM_BANKS]; 165 u64 size[CONFIG_NR_DRAM_BANKS]; 166 167 /* fixup DT for the two DDR banks */ 168 base[0] = gd->bd->bi_dram[0].start; 169 size[0] = gd->bd->bi_dram[0].size; 170 base[1] = gd->bd->bi_dram[1].start; 171 size[1] = gd->bd->bi_dram[1].size; 172 173 fdt_fixup_memory_banks(blob, base, size, 2); 174 ft_cpu_setup(blob, bd); 175 176 #ifdef CONFIG_SYS_DPAA_FMAN 177 fdt_fixup_fman_ethernet(blob); 178 #endif 179 180 /* 181 * qe-hdlc and usb multi-use the pins, 182 * when set hwconfig to qe-hdlc, delete usb node. 183 */ 184 if (hwconfig("qe-hdlc")) 185 #ifdef CONFIG_HAS_FSL_XHCI_USB 186 fdt_del_node_and_alias(blob, "usb1"); 187 #endif 188 /* 189 * qe just support qe-uart and qe-hdlc, 190 * if qe-uart and qe-hdlc are not set in hwconfig, 191 * delete qe node. 192 */ 193 if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc")) 194 fdt_del_qe(blob); 195 196 return 0; 197 } 198 199 u8 flash_read8(void *addr) 200 { 201 return __raw_readb(addr + 1); 202 } 203 204 void flash_write16(u16 val, void *addr) 205 { 206 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 207 208 __raw_writew(shftval, addr); 209 } 210 211 u16 flash_read16(void *addr) 212 { 213 u16 val = __raw_readw(addr); 214 215 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 216 } 217 218 #endif 219