1 /*
2  * Copyright 2015 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <i2c.h>
9 #include <asm/io.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/soc.h>
13 #include <fdt_support.h>
14 #include <hwconfig.h>
15 #include <ahci.h>
16 #include <mmc.h>
17 #include <scsi.h>
18 #include <fm_eth.h>
19 #include <fsl_esdhc.h>
20 #include <fsl_ifc.h>
21 #include <fsl_sec.h>
22 #include "cpld.h"
23 #ifdef CONFIG_U_QE
24 #include <fsl_qe.h>
25 #endif
26 #include <asm/arch/ppa.h>
27 
28 DECLARE_GLOBAL_DATA_PTR;
29 
30 int board_early_init_f(void)
31 {
32 	fsl_lsch2_early_init_f();
33 
34 	return 0;
35 }
36 
37 #ifndef CONFIG_SPL_BUILD
38 
39 int checkboard(void)
40 {
41 	static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
42 #ifndef CONFIG_SD_BOOT
43 	u8 cfg_rcw_src1, cfg_rcw_src2;
44 	u16 cfg_rcw_src;
45 #endif
46 	u8 sd1refclk_sel;
47 
48 	printf("Board: LS1043ARDB, boot from ");
49 
50 #ifdef CONFIG_SD_BOOT
51 	puts("SD\n");
52 #else
53 	cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
54 	cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
55 	cpld_rev_bit(&cfg_rcw_src1);
56 	cfg_rcw_src = cfg_rcw_src1;
57 	cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
58 
59 	if (cfg_rcw_src == 0x25)
60 		printf("vBank %d\n", CPLD_READ(vbank));
61 	else if (cfg_rcw_src == 0x106)
62 		puts("NAND\n");
63 	else
64 		printf("Invalid setting of SW4\n");
65 #endif
66 
67 	printf("CPLD:  V%x.%x\nPCBA:  V%x.0\n", CPLD_READ(cpld_ver),
68 	       CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
69 
70 	puts("SERDES Reference Clocks:\n");
71 	sd1refclk_sel = CPLD_READ(sd1refclk_sel);
72 	printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
73 
74 	return 0;
75 }
76 
77 int board_init(void)
78 {
79 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
80 
81 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
82 	erratum_a010315();
83 #endif
84 
85 #ifdef CONFIG_FSL_IFC
86 	init_final_memctl_regs();
87 #endif
88 
89 #ifdef CONFIG_SECURE_BOOT
90 	/* In case of Secure Boot, the IBR configures the SMMU
91 	 * to allow only Secure transactions.
92 	 * SMMU must be reset in bypass mode.
93 	 * Set the ClientPD bit and Clear the USFCFG Bit
94 	 */
95 	u32 val;
96 	val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
97 	out_le32(SMMU_SCR0, val);
98 	val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
99 	out_le32(SMMU_NSCR0, val);
100 #endif
101 
102 #ifdef CONFIG_FSL_CAAM
103 	sec_init();
104 #endif
105 
106 #ifdef CONFIG_FSL_LS_PPA
107 	ppa_init();
108 #endif
109 
110 #ifdef CONFIG_U_QE
111 	u_qe_init();
112 #endif
113 	/* invert AQR105 IRQ pins polarity */
114 	out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
115 
116 	return 0;
117 }
118 
119 int config_board_mux(void)
120 {
121 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
122 	u32 usb_pwrfault;
123 
124 	if (hwconfig("qe-hdlc")) {
125 		out_be32(&scfg->rcwpmuxcr0,
126 			 (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
127 		printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
128 		       in_be32(&scfg->rcwpmuxcr0));
129 	} else {
130 #ifdef CONFIG_HAS_FSL_XHCI_USB
131 		out_be32(&scfg->rcwpmuxcr0, 0x3333);
132 		out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
133 		usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
134 				SCFG_USBPWRFAULT_USB3_SHIFT) |
135 				(SCFG_USBPWRFAULT_DEDICATED <<
136 				SCFG_USBPWRFAULT_USB2_SHIFT) |
137 				(SCFG_USBPWRFAULT_SHARED <<
138 				 SCFG_USBPWRFAULT_USB1_SHIFT);
139 		out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
140 #endif
141 	}
142 	return 0;
143 }
144 
145 #if defined(CONFIG_MISC_INIT_R)
146 int misc_init_r(void)
147 {
148 	config_board_mux();
149 	return 0;
150 }
151 #endif
152 
153 void fdt_del_qe(void *blob)
154 {
155 	int nodeoff = 0;
156 
157 	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
158 				"fsl,qe")) >= 0) {
159 		fdt_del_node(blob, nodeoff);
160 	}
161 }
162 
163 int ft_board_setup(void *blob, bd_t *bd)
164 {
165 	u64 base[CONFIG_NR_DRAM_BANKS];
166 	u64 size[CONFIG_NR_DRAM_BANKS];
167 
168 	/* fixup DT for the two DDR banks */
169 	base[0] = gd->bd->bi_dram[0].start;
170 	size[0] = gd->bd->bi_dram[0].size;
171 	base[1] = gd->bd->bi_dram[1].start;
172 	size[1] = gd->bd->bi_dram[1].size;
173 
174 	fdt_fixup_memory_banks(blob, base, size, 2);
175 	ft_cpu_setup(blob, bd);
176 
177 #ifdef CONFIG_SYS_DPAA_FMAN
178 	fdt_fixup_fman_ethernet(blob);
179 #endif
180 
181 	/*
182 	 * qe-hdlc and usb multi-use the pins,
183 	 * when set hwconfig to qe-hdlc, delete usb node.
184 	 */
185 	if (hwconfig("qe-hdlc"))
186 #ifdef CONFIG_HAS_FSL_XHCI_USB
187 		fdt_del_node_and_alias(blob, "usb1");
188 #endif
189 	/*
190 	 * qe just support qe-uart and qe-hdlc,
191 	 * if qe-uart and qe-hdlc are not set in hwconfig,
192 	 * delete qe node.
193 	 */
194 	if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
195 		fdt_del_qe(blob);
196 
197 	return 0;
198 }
199 
200 u8 flash_read8(void *addr)
201 {
202 	return __raw_readb(addr + 1);
203 }
204 
205 void flash_write16(u16 val, void *addr)
206 {
207 	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
208 
209 	__raw_writew(shftval, addr);
210 }
211 
212 u16 flash_read16(void *addr)
213 {
214 	u16 val = __raw_readw(addr);
215 
216 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
217 }
218 
219 #endif
220