1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/fsl_serdes.h> 12 #include <asm/arch/soc.h> 13 #include <hwconfig.h> 14 #include <ahci.h> 15 #include <mmc.h> 16 #include <scsi.h> 17 #include <fm_eth.h> 18 #include <fsl_csu.h> 19 #include <fsl_esdhc.h> 20 #include <fsl_ifc.h> 21 #include <environment.h> 22 #include <fsl_sec.h> 23 #include "cpld.h" 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 int checkboard(void) 28 { 29 static const char *freq[3] = {"100.00MHZ", "156.25MHZ"}; 30 #ifndef CONFIG_SD_BOOT 31 u8 cfg_rcw_src1, cfg_rcw_src2; 32 u32 cfg_rcw_src; 33 #endif 34 u32 sd1refclk_sel; 35 36 printf("Board: LS1043ARDB, boot from "); 37 38 #ifdef CONFIG_SD_BOOT 39 puts("SD\n"); 40 #else 41 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); 42 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); 43 cpld_rev_bit(&cfg_rcw_src1); 44 cfg_rcw_src = cfg_rcw_src1; 45 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; 46 47 if (cfg_rcw_src == 0x25) 48 printf("vBank %d\n", CPLD_READ(vbank)); 49 else if (cfg_rcw_src == 0x106) 50 puts("NAND\n"); 51 else 52 printf("Invalid setting of SW4\n"); 53 #endif 54 55 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), 56 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); 57 58 puts("SERDES Reference Clocks:\n"); 59 sd1refclk_sel = CPLD_READ(sd1refclk_sel); 60 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); 61 62 return 0; 63 } 64 65 int dram_init(void) 66 { 67 gd->ram_size = initdram(0); 68 69 return 0; 70 } 71 72 int board_early_init_f(void) 73 { 74 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 75 u32 usb_pwrfault; 76 77 fsl_lsch2_early_init_f(); 78 79 #ifdef CONFIG_HAS_FSL_XHCI_USB 80 out_be32(&scfg->rcwpmuxcr0, 0x3333); 81 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); 82 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << 83 SCFG_USBPWRFAULT_USB3_SHIFT) | 84 (SCFG_USBPWRFAULT_DEDICATED << 85 SCFG_USBPWRFAULT_USB2_SHIFT) | 86 (SCFG_USBPWRFAULT_SHARED << 87 SCFG_USBPWRFAULT_USB1_SHIFT); 88 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); 89 #endif 90 91 return 0; 92 } 93 94 int board_init(void) 95 { 96 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 97 98 /* 99 * Set CCI-400 control override register to enable barrier 100 * transaction 101 */ 102 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 103 104 #ifdef CONFIG_FSL_IFC 105 init_final_memctl_regs(); 106 #endif 107 108 #ifdef CONFIG_ENV_IS_NOWHERE 109 gd->env_addr = (ulong)&default_environment[0]; 110 #endif 111 112 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 113 enable_layerscape_ns_access(); 114 #endif 115 116 return 0; 117 } 118 119 int config_board_mux(void) 120 { 121 return 0; 122 } 123 124 #if defined(CONFIG_MISC_INIT_R) 125 int misc_init_r(void) 126 { 127 config_board_mux(); 128 #ifdef CONFIG_SECURE_BOOT 129 /* In case of Secure Boot, the IBR configures the SMMU 130 * to allow only Secure transactions. 131 * SMMU must be reset in bypass mode. 132 * Set the ClientPD bit and Clear the USFCFG Bit 133 */ 134 u32 val; 135 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 136 out_le32(SMMU_SCR0, val); 137 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); 138 out_le32(SMMU_NSCR0, val); 139 #endif 140 #ifdef CONFIG_FSL_CAAM 141 return sec_init(); 142 #endif 143 return 0; 144 } 145 #endif 146 147 int ft_board_setup(void *blob, bd_t *bd) 148 { 149 u64 base[CONFIG_NR_DRAM_BANKS]; 150 u64 size[CONFIG_NR_DRAM_BANKS]; 151 152 /* fixup DT for the two DDR banks */ 153 base[0] = gd->bd->bi_dram[0].start; 154 size[0] = gd->bd->bi_dram[0].size; 155 base[1] = gd->bd->bi_dram[1].start; 156 size[1] = gd->bd->bi_dram[1].size; 157 158 fdt_fixup_memory_banks(blob, base, size, 2); 159 ft_cpu_setup(blob, bd); 160 161 #ifdef CONFIG_SYS_DPAA_FMAN 162 fdt_fixup_fman_ethernet(blob); 163 #endif 164 return 0; 165 } 166 167 u8 flash_read8(void *addr) 168 { 169 return __raw_readb(addr + 1); 170 } 171 172 void flash_write16(u16 val, void *addr) 173 { 174 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 175 176 __raw_writew(shftval, addr); 177 } 178 179 u16 flash_read16(void *addr) 180 { 181 u16 val = __raw_readw(addr); 182 183 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 184 } 185