1 /*
2  * Copyright 2015 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __DDR_H__
8 #define __DDR_H__
9 
10 extern void erratum_a008850_post(void);
11 
12 struct board_specific_parameters {
13 	u32 n_ranks;
14 	u32 datarate_mhz_high;
15 	u32 rank_gb;
16 	u32 clk_adjust;
17 	u32 wrlvl_start;
18 	u32 wrlvl_ctl_2;
19 	u32 wrlvl_ctl_3;
20 	u32 cpo_override;
21 	u32 write_data_delay;
22 	u32 force_2t;
23 };
24 
25 /*
26  * These tables contain all valid speeds we want to override with board
27  * specific parameters. datarate_mhz_high values need to be in ascending order
28  * for each n_ranks group.
29  */
30 static const struct board_specific_parameters udimm0[] = {
31 	/*
32 	 * memory controller 0
33 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
34 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
35 	 */
36 #ifdef CONFIG_SYS_FSL_DDR4
37 	{1,  1666, 0, 12,     7, 0x07090800, 0x00000000,},
38 	{1,  1900, 0, 12,     7, 0x07090800, 0x00000000,},
39 	{1,  2200, 0, 12,     7, 0x07090800, 0x00000000,},
40 #endif
41 	{}
42 };
43 
44 static const struct board_specific_parameters *udimms[] = {
45 	udimm0,
46 };
47 
48 #ifndef CONFIG_SYS_DDR_RAW_TIMING
49 fsl_ddr_cfg_regs_t ddr_cfg_regs_1600 = {
50 	.cs[0].bnds = 0x0000007F,
51 	.cs[1].bnds = 0,
52 	.cs[2].bnds = 0,
53 	.cs[3].bnds = 0,
54 	.cs[0].config = 0x80040322,
55 	.cs[0].config_2 = 0,
56 	.cs[1].config = 0,
57 	.cs[1].config_2 = 0,
58 	.cs[2].config = 0,
59 	.cs[3].config = 0,
60 	.timing_cfg_3 = 0x010C1000,
61 	.timing_cfg_0 = 0x91550018,
62 	.timing_cfg_1 = 0xBBB48C42,
63 	.timing_cfg_2 = 0x0048C111,
64 	.ddr_sdram_cfg = 0xC50C0008,
65 	.ddr_sdram_cfg_2 = 0x00401100,
66 	.ddr_sdram_cfg_3 = 0,
67 	.ddr_sdram_mode = 0x03010210,
68 	.ddr_sdram_mode_2 = 0,
69 	.ddr_sdram_mode_3 = 0x00010210,
70 	.ddr_sdram_mode_4 = 0,
71 	.ddr_sdram_mode_5 = 0x00010210,
72 	.ddr_sdram_mode_6 = 0,
73 	.ddr_sdram_mode_7 = 0x00010210,
74 	.ddr_sdram_mode_8 = 0,
75 	.ddr_sdram_mode_9 = 0x00000500,
76 	.ddr_sdram_mode_10 = 0x04000000,
77 	.ddr_sdram_mode_11 = 0x00000400,
78 	.ddr_sdram_mode_12 = 0x04000000,
79 	.ddr_sdram_mode_13 = 0x00000400,
80 	.ddr_sdram_mode_14 = 0x04000000,
81 	.ddr_sdram_mode_15 = 0x00000400,
82 	.ddr_sdram_mode_16 = 0x04000000,
83 	.ddr_sdram_interval = 0x18600618,
84 	.ddr_data_init = 0xDEADBEEF,
85 	.ddr_sdram_clk_cntl = 0x03000000,
86 	.ddr_init_addr = 0,
87 	.ddr_init_ext_addr = 0,
88 	.timing_cfg_4 = 0x00000002,
89 	.timing_cfg_5 = 0x03401400,
90 	.timing_cfg_6 = 0,
91 	.timing_cfg_7 = 0x13300000,
92 	.timing_cfg_8 = 0x02115600,
93 	.timing_cfg_9 = 0,
94 	.ddr_zq_cntl = 0x8A090705,
95 	.ddr_wrlvl_cntl = 0x8675F607,
96 	.ddr_wrlvl_cntl_2 = 0x07090800,
97 	.ddr_wrlvl_cntl_3 = 0,
98 	.ddr_sr_cntr = 0,
99 	.ddr_sdram_rcw_1 = 0,
100 	.ddr_sdram_rcw_2 = 0,
101 	.ddr_cdr1 = 0x80040000,
102 	.ddr_cdr2 = 0x0000A181,
103 	.dq_map_0 = 0,
104 	.dq_map_1 = 0,
105 	.dq_map_2 = 0,
106 	.dq_map_3 = 0,
107 	.debug[28] = 0x00700046,
108 
109 };
110 
111 fixed_ddr_parm_t fixed_ddr_parm_0[] = {
112 	{1550, 1650, &ddr_cfg_regs_1600},
113 	{0, 0, NULL}
114 };
115 
116 #endif
117 #endif
118