1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2015 Freescale Semiconductor 4 * 5 * Freescale LS1043ARDB board-specific CPLD controlling supports. 6 */ 7 8 #include <common.h> 9 #include <command.h> 10 #include <asm/io.h> 11 #include "cpld.h" 12 13 u8 cpld_read(unsigned int reg) 14 { 15 void *p = (void *)CONFIG_SYS_CPLD_BASE; 16 17 return in_8(p + reg); 18 } 19 20 void cpld_write(unsigned int reg, u8 value) 21 { 22 void *p = (void *)CONFIG_SYS_CPLD_BASE; 23 24 out_8(p + reg, value); 25 } 26 27 /* Set the boot bank to the alternate bank */ 28 void cpld_set_altbank(void) 29 { 30 u16 reg = CPLD_CFG_RCW_SRC_NOR; 31 u8 reg4 = CPLD_READ(soft_mux_on); 32 u8 reg5 = (u8)(reg >> 1); 33 u8 reg6 = (u8)(reg & 1); 34 u8 reg7 = CPLD_READ(vbank); 35 36 cpld_rev_bit(®5); 37 38 CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); 39 40 CPLD_WRITE(cfg_rcw_src1, reg5); 41 CPLD_WRITE(cfg_rcw_src2, reg6); 42 43 reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; 44 CPLD_WRITE(vbank, reg7); 45 46 CPLD_WRITE(system_rst, 1); 47 } 48 49 /* Set the boot bank to the default bank */ 50 void cpld_set_defbank(void) 51 { 52 u16 reg = CPLD_CFG_RCW_SRC_NOR; 53 u8 reg4 = CPLD_READ(soft_mux_on); 54 u8 reg5 = (u8)(reg >> 1); 55 u8 reg6 = (u8)(reg & 1); 56 57 cpld_rev_bit(®5); 58 59 CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); 60 61 CPLD_WRITE(cfg_rcw_src1, reg5); 62 CPLD_WRITE(cfg_rcw_src2, reg6); 63 64 CPLD_WRITE(vbank, 0); 65 66 CPLD_WRITE(system_rst, 1); 67 } 68 69 void cpld_set_nand(void) 70 { 71 u16 reg = CPLD_CFG_RCW_SRC_NAND; 72 u8 reg5 = (u8)(reg >> 1); 73 u8 reg6 = (u8)(reg & 1); 74 75 cpld_rev_bit(®5); 76 77 CPLD_WRITE(soft_mux_on, 1); 78 79 CPLD_WRITE(cfg_rcw_src1, reg5); 80 CPLD_WRITE(cfg_rcw_src2, reg6); 81 82 CPLD_WRITE(system_rst, 1); 83 } 84 85 void cpld_set_sd(void) 86 { 87 u16 reg = CPLD_CFG_RCW_SRC_SD; 88 u8 reg5 = (u8)(reg >> 1); 89 u8 reg6 = (u8)(reg & 1); 90 91 cpld_rev_bit(®5); 92 93 CPLD_WRITE(soft_mux_on, 1); 94 95 CPLD_WRITE(cfg_rcw_src1, reg5); 96 CPLD_WRITE(cfg_rcw_src2, reg6); 97 98 CPLD_WRITE(system_rst, 1); 99 } 100 #ifdef DEBUG 101 static void cpld_dump_regs(void) 102 { 103 printf("cpld_ver = %x\n", CPLD_READ(cpld_ver)); 104 printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub)); 105 printf("pcba_ver = %x\n", CPLD_READ(pcba_ver)); 106 printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on)); 107 printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1)); 108 printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2)); 109 printf("vbank = %x\n", CPLD_READ(vbank)); 110 printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel)); 111 printf("uart_sel = %x\n", CPLD_READ(uart_sel)); 112 printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel)); 113 printf("tdmclk_mux_sel = %x\n", CPLD_READ(tdmclk_mux_sel)); 114 printf("sdhc_spics_sel = %x\n", CPLD_READ(sdhc_spics_sel)); 115 printf("status_led = %x\n", CPLD_READ(status_led)); 116 putc('\n'); 117 } 118 #endif 119 120 void cpld_rev_bit(unsigned char *value) 121 { 122 u8 rev_val, val; 123 int i; 124 125 val = *value; 126 rev_val = val & 1; 127 for (i = 1; i <= 7; i++) { 128 val >>= 1; 129 rev_val <<= 1; 130 rev_val |= val & 1; 131 } 132 133 *value = rev_val; 134 } 135 136 int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 137 { 138 int rc = 0; 139 140 if (argc <= 1) 141 return cmd_usage(cmdtp); 142 143 if (strcmp(argv[1], "reset") == 0) { 144 if (strcmp(argv[2], "altbank") == 0) 145 cpld_set_altbank(); 146 else if (strcmp(argv[2], "nand") == 0) 147 cpld_set_nand(); 148 else if (strcmp(argv[2], "sd") == 0) 149 cpld_set_sd(); 150 else 151 cpld_set_defbank(); 152 #ifdef DEBUG 153 } else if (strcmp(argv[1], "dump") == 0) { 154 cpld_dump_regs(); 155 #endif 156 } else { 157 rc = cmd_usage(cmdtp); 158 } 159 160 return rc; 161 } 162 163 U_BOOT_CMD( 164 cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, 165 "Reset the board or alternate bank", 166 "reset: reset to default bank\n" 167 "cpld reset altbank: reset to alternate bank\n" 168 "cpld reset nand: reset to boot from NAND flash\n" 169 "cpld reset sd: reset to boot from SD card\n" 170 #ifdef DEBUG 171 "cpld dump - display the CPLD registers\n" 172 #endif 173 ); 174