1 /* 2 * Copyright 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Freescale LS1043ARDB board-specific CPLD controlling supports. 7 */ 8 9 #include <common.h> 10 #include <command.h> 11 #include <asm/io.h> 12 #include "cpld.h" 13 14 u8 cpld_read(unsigned int reg) 15 { 16 void *p = (void *)CONFIG_SYS_CPLD_BASE; 17 18 return in_8(p + reg); 19 } 20 21 void cpld_write(unsigned int reg, u8 value) 22 { 23 void *p = (void *)CONFIG_SYS_CPLD_BASE; 24 25 out_8(p + reg, value); 26 } 27 28 /* Set the boot bank to the alternate bank */ 29 void cpld_set_altbank(void) 30 { 31 u8 reg4 = CPLD_READ(soft_mux_on); 32 u8 reg7 = CPLD_READ(vbank); 33 34 CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL); 35 36 reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; 37 CPLD_WRITE(vbank, reg7); 38 39 CPLD_WRITE(system_rst, 1); 40 } 41 42 /* Set the boot bank to the default bank */ 43 void cpld_set_defbank(void) 44 { 45 CPLD_WRITE(global_rst, 1); 46 } 47 48 void cpld_set_nand(void) 49 { 50 u16 reg = CPLD_CFG_RCW_SRC_NAND; 51 u8 reg5 = (u8)(reg >> 1); 52 u8 reg6 = (u8)(reg & 1); 53 54 cpld_rev_bit(®5); 55 56 CPLD_WRITE(soft_mux_on, 1); 57 58 CPLD_WRITE(cfg_rcw_src1, reg5); 59 CPLD_WRITE(cfg_rcw_src2, reg6); 60 61 CPLD_WRITE(system_rst, 1); 62 } 63 64 void cpld_set_sd(void) 65 { 66 u16 reg = CPLD_CFG_RCW_SRC_SD; 67 u8 reg5 = (u8)(reg >> 1); 68 u8 reg6 = (u8)(reg & 1); 69 70 cpld_rev_bit(®5); 71 72 CPLD_WRITE(soft_mux_on, 1); 73 74 CPLD_WRITE(cfg_rcw_src1, reg5); 75 CPLD_WRITE(cfg_rcw_src2, reg6); 76 77 CPLD_WRITE(system_rst, 1); 78 } 79 #ifdef DEBUG 80 static void cpld_dump_regs(void) 81 { 82 printf("cpld_ver = %x\n", CPLD_READ(cpld_ver)); 83 printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub)); 84 printf("pcba_ver = %x\n", CPLD_READ(pcba_ver)); 85 printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on)); 86 printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1)); 87 printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2)); 88 printf("vbank = %x\n", CPLD_READ(vbank)); 89 printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel)); 90 printf("uart_sel = %x\n", CPLD_READ(uart_sel)); 91 printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel)); 92 printf("tdmclk_mux_sel = %x\n", CPLD_READ(tdmclk_mux_sel)); 93 printf("sdhc_spics_sel = %x\n", CPLD_READ(sdhc_spics_sel)); 94 printf("status_led = %x\n", CPLD_READ(status_led)); 95 putc('\n'); 96 } 97 #endif 98 99 void cpld_rev_bit(unsigned char *value) 100 { 101 u8 rev_val, val; 102 int i; 103 104 val = *value; 105 rev_val = val & 1; 106 for (i = 1; i <= 7; i++) { 107 val >>= 1; 108 rev_val <<= 1; 109 rev_val |= val & 1; 110 } 111 112 *value = rev_val; 113 } 114 115 int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 116 { 117 int rc = 0; 118 119 if (argc <= 1) 120 return cmd_usage(cmdtp); 121 122 if (strcmp(argv[1], "reset") == 0) { 123 if (strcmp(argv[2], "altbank") == 0) 124 cpld_set_altbank(); 125 else if (strcmp(argv[2], "nand") == 0) 126 cpld_set_nand(); 127 else if (strcmp(argv[2], "sd") == 0) 128 cpld_set_sd(); 129 else 130 cpld_set_defbank(); 131 #ifdef DEBUG 132 } else if (strcmp(argv[1], "dump") == 0) { 133 cpld_dump_regs(); 134 #endif 135 } else { 136 rc = cmd_usage(cmdtp); 137 } 138 139 return rc; 140 } 141 142 U_BOOT_CMD( 143 cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, 144 "Reset the board or alternate bank", 145 "reset: reset to default bank\n" 146 "cpld reset altbank: reset to alternate bank\n" 147 "cpld reset nand: reset to boot from NAND flash\n" 148 "cpld reset sd: reset to boot from SD card\n" 149 #ifdef DEBUG 150 "cpld dump - display the CPLD registers\n" 151 #endif 152 ); 153