1 /*
2  * Copyright 2015 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __LS1043AQDS_QIXIS_H__
8 #define __LS1043AQDS_QIXIS_H__
9 
10 /* Definitions of QIXIS Registers for LS1043AQDS */
11 
12 /* BRDCFG4[4:7] select EC1 and EC2 as a pair */
13 #define BRDCFG4_EMISEL_MASK		0xe0
14 #define BRDCFG4_EMISEL_SHIFT		5
15 
16 /* SYSCLK */
17 #define QIXIS_SYSCLK_66			0x0
18 #define QIXIS_SYSCLK_83			0x1
19 #define QIXIS_SYSCLK_100		0x2
20 #define QIXIS_SYSCLK_125		0x3
21 #define QIXIS_SYSCLK_133		0x4
22 #define QIXIS_SYSCLK_150		0x5
23 #define QIXIS_SYSCLK_160		0x6
24 #define QIXIS_SYSCLK_166		0x7
25 #define QIXIS_SYSCLK_64			0x8
26 
27 /* DDRCLK */
28 #define QIXIS_DDRCLK_66			0x0
29 #define QIXIS_DDRCLK_100		0x1
30 #define QIXIS_DDRCLK_125		0x2
31 #define QIXIS_DDRCLK_133		0x3
32 
33 /* BRDCFG2 - SD clock*/
34 #define QIXIS_SDCLK1_100		0x0
35 #define QIXIS_SDCLK1_125		0x1
36 #define QIXIS_SDCLK1_165		0x2
37 #define QIXIS_SDCLK1_100_SP		0x3
38 
39 #endif
40