1 /*
2  * Copyright 2015 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <i2c.h>
9 #include <fdt_support.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/fdt.h>
14 #include <asm/arch/mmu.h>
15 #include <asm/arch/soc.h>
16 #include <ahci.h>
17 #include <hwconfig.h>
18 #include <mmc.h>
19 #include <scsi.h>
20 #include <fm_eth.h>
21 #include <fsl_esdhc.h>
22 #include <fsl_ifc.h>
23 #include <spl.h>
24 
25 #include "../common/qixis.h"
26 #include "ls1043aqds_qixis.h"
27 
28 DECLARE_GLOBAL_DATA_PTR;
29 
30 enum {
31 	MUX_TYPE_GPIO,
32 };
33 
34 /* LS1043AQDS serdes mux */
35 #define CFG_SD_MUX1_SLOT2	0x0 /* SLOT2 TX/RX0 */
36 #define CFG_SD_MUX1_SLOT1	0x1 /* SLOT1 TX/RX1 */
37 #define CFG_SD_MUX2_SLOT3	0x0 /* SLOT3 TX/RX0 */
38 #define CFG_SD_MUX2_SLOT1	0x1 /* SLOT1 TX/RX2 */
39 #define CFG_SD_MUX3_SLOT4	0x0 /* SLOT4 TX/RX0 */
40 #define CFG_SD_MUX3_MUX4	0x1 /* MUX4 */
41 #define CFG_SD_MUX4_SLOT3	0x0 /* SLOT3 TX/RX1 */
42 #define CFG_SD_MUX4_SLOT1	0x1 /* SLOT1 TX/RX3 */
43 #define CFG_UART_MUX_MASK	0x6
44 #define CFG_UART_MUX_SHIFT	1
45 #define CFG_LPUART_EN		0x1
46 
47 int checkboard(void)
48 {
49 	char buf[64];
50 #ifndef CONFIG_SD_BOOT
51 	u8 sw;
52 #endif
53 
54 	puts("Board: LS1043AQDS, boot from ");
55 
56 #ifdef CONFIG_SD_BOOT
57 	puts("SD\n");
58 #else
59 	sw = QIXIS_READ(brdcfg[0]);
60 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
61 
62 	if (sw < 0x8)
63 		printf("vBank: %d\n", sw);
64 	else if (sw == 0x8)
65 		puts("PromJet\n");
66 	else if (sw == 0x9)
67 		puts("NAND\n");
68 	else if (sw == 0xF)
69 		printf("QSPI\n");
70 	else
71 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
72 #endif
73 
74 	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
75 	       QIXIS_READ(id), QIXIS_READ(arch));
76 
77 	printf("FPGA:  v%d (%s), build %d\n",
78 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
79 	       (int)qixis_read_minor());
80 
81 	return 0;
82 }
83 
84 bool if_board_diff_clk(void)
85 {
86 	u8 diff_conf = QIXIS_READ(brdcfg[11]);
87 
88 	return diff_conf & 0x40;
89 }
90 
91 unsigned long get_board_sys_clk(void)
92 {
93 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
94 
95 	switch (sysclk_conf & 0x0f) {
96 	case QIXIS_SYSCLK_64:
97 		return 64000000;
98 	case QIXIS_SYSCLK_83:
99 		return 83333333;
100 	case QIXIS_SYSCLK_100:
101 		return 100000000;
102 	case QIXIS_SYSCLK_125:
103 		return 125000000;
104 	case QIXIS_SYSCLK_133:
105 		return 133333333;
106 	case QIXIS_SYSCLK_150:
107 		return 150000000;
108 	case QIXIS_SYSCLK_160:
109 		return 160000000;
110 	case QIXIS_SYSCLK_166:
111 		return 166666666;
112 	}
113 
114 	return 66666666;
115 }
116 
117 unsigned long get_board_ddr_clk(void)
118 {
119 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
120 
121 	if (if_board_diff_clk())
122 		return get_board_sys_clk();
123 	switch ((ddrclk_conf & 0x30) >> 4) {
124 	case QIXIS_DDRCLK_100:
125 		return 100000000;
126 	case QIXIS_DDRCLK_125:
127 		return 125000000;
128 	case QIXIS_DDRCLK_133:
129 		return 133333333;
130 	}
131 
132 	return 66666666;
133 }
134 
135 int select_i2c_ch_pca9547(u8 ch)
136 {
137 	int ret;
138 
139 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
140 	if (ret) {
141 		puts("PCA: failed to select proper channel\n");
142 		return ret;
143 	}
144 
145 	return 0;
146 }
147 
148 int dram_init(void)
149 {
150 	/*
151 	 * When resuming from deep sleep, the I2C channel may not be
152 	 * in the default channel. So, switch to the default channel
153 	 * before accessing DDR SPD.
154 	 */
155 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
156 	initdram();
157 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
158 	/* This will break-before-make MMU for DDR */
159 	update_early_mmu_table();
160 #endif
161 
162 	return 0;
163 }
164 
165 int i2c_multiplexer_select_vid_channel(u8 channel)
166 {
167 	return select_i2c_ch_pca9547(channel);
168 }
169 
170 void board_retimer_init(void)
171 {
172 	u8 reg;
173 
174 	/* Retimer is connected to I2C1_CH7_CH5 */
175 	select_i2c_ch_pca9547(I2C_MUX_CH7);
176 	reg = I2C_MUX_CH5;
177 	i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
178 
179 	/* Access to Control/Shared register */
180 	reg = 0x0;
181 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
182 
183 	/* Read device revision and ID */
184 	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
185 	debug("Retimer version id = 0x%x\n", reg);
186 
187 	/* Enable Broadcast. All writes target all channel register sets */
188 	reg = 0x0c;
189 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
190 
191 	/* Reset Channel Registers */
192 	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
193 	reg |= 0x4;
194 	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
195 
196 	/* Enable override divider select and Enable Override Output Mux */
197 	i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
198 	reg |= 0x24;
199 	i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
200 
201 	/* Select VCO Divider to full rate (000) */
202 	i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
203 	reg &= 0x8f;
204 	i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
205 
206 	/* Selects active PFD MUX Input as Re-timed Data (001) */
207 	i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
208 	reg &= 0x3f;
209 	reg |= 0x20;
210 	i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
211 
212 	/* Set data rate as 10.3125 Gbps */
213 	reg = 0x0;
214 	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
215 	reg = 0xb2;
216 	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
217 	reg = 0x90;
218 	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
219 	reg = 0xb3;
220 	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
221 	reg = 0xcd;
222 	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
223 
224 	/* Return the default channel */
225 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
226 }
227 
228 int board_early_init_f(void)
229 {
230 #ifdef CONFIG_HAS_FSL_XHCI_USB
231 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
232 	u32 usb_pwrfault;
233 #endif
234 #ifdef CONFIG_LPUART
235 	u8 uart;
236 #endif
237 
238 #ifdef CONFIG_SYS_I2C_EARLY_INIT
239 	i2c_early_init_f();
240 #endif
241 	fsl_lsch2_early_init_f();
242 
243 #ifdef CONFIG_HAS_FSL_XHCI_USB
244 	out_be32(&scfg->rcwpmuxcr0, 0x3333);
245 	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
246 	usb_pwrfault =
247 		(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
248 		(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
249 		(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
250 	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
251 #endif
252 
253 #ifdef CONFIG_LPUART
254 	/* We use lpuart0 as system console */
255 	uart = QIXIS_READ(brdcfg[14]);
256 	uart &= ~CFG_UART_MUX_MASK;
257 	uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
258 	QIXIS_WRITE(brdcfg[14], uart);
259 #endif
260 
261 	return 0;
262 }
263 
264 #ifdef CONFIG_FSL_DEEP_SLEEP
265 /* determine if it is a warm boot */
266 bool is_warm_boot(void)
267 {
268 #define DCFG_CCSR_CRSTSR_WDRFR	(1 << 3)
269 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
270 
271 	if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
272 		return 1;
273 
274 	return 0;
275 }
276 #endif
277 
278 int config_board_mux(int ctrl_type)
279 {
280 	u8 reg14;
281 
282 	reg14 = QIXIS_READ(brdcfg[14]);
283 
284 	switch (ctrl_type) {
285 	case MUX_TYPE_GPIO:
286 		reg14 = (reg14 & (~0x30)) | 0x20;
287 		break;
288 	default:
289 		puts("Unsupported mux interface type\n");
290 		return -1;
291 	}
292 
293 	QIXIS_WRITE(brdcfg[14], reg14);
294 
295 	return 0;
296 }
297 
298 int config_serdes_mux(void)
299 {
300 	return 0;
301 }
302 
303 
304 #ifdef CONFIG_MISC_INIT_R
305 int misc_init_r(void)
306 {
307 	if (hwconfig("gpio"))
308 		config_board_mux(MUX_TYPE_GPIO);
309 
310 	return 0;
311 }
312 #endif
313 
314 int board_init(void)
315 {
316 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
317 	erratum_a010315();
318 #endif
319 
320 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
321 	board_retimer_init();
322 
323 #ifdef CONFIG_SYS_FSL_SERDES
324 	config_serdes_mux();
325 #endif
326 
327 	return 0;
328 }
329 
330 #ifdef CONFIG_OF_BOARD_SETUP
331 int ft_board_setup(void *blob, bd_t *bd)
332 {
333 	u64 base[CONFIG_NR_DRAM_BANKS];
334 	u64 size[CONFIG_NR_DRAM_BANKS];
335 	u8 reg;
336 
337 	/* fixup DT for the two DDR banks */
338 	base[0] = gd->bd->bi_dram[0].start;
339 	size[0] = gd->bd->bi_dram[0].size;
340 	base[1] = gd->bd->bi_dram[1].start;
341 	size[1] = gd->bd->bi_dram[1].size;
342 
343 	fdt_fixup_memory_banks(blob, base, size, 2);
344 	ft_cpu_setup(blob, bd);
345 
346 #ifdef CONFIG_SYS_DPAA_FMAN
347 	fdt_fixup_fman_ethernet(blob);
348 	fdt_fixup_board_enet(blob);
349 #endif
350 
351 	reg = QIXIS_READ(brdcfg[0]);
352 	reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
353 
354 	/* Disable IFC if QSPI is enabled */
355 	if (reg == 0xF)
356 		do_fixup_by_compat(blob, "fsl,ifc",
357 				   "status", "disabled", 8 + 1, 1);
358 
359 	return 0;
360 }
361 #endif
362 
363 u8 flash_read8(void *addr)
364 {
365 	return __raw_readb(addr + 1);
366 }
367 
368 void flash_write16(u16 val, void *addr)
369 {
370 	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
371 
372 	__raw_writew(shftval, addr);
373 }
374 
375 u16 flash_read16(void *addr)
376 {
377 	u16 val = __raw_readw(addr);
378 
379 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
380 }
381