1 /*
2  * Copyright 2015 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <i2c.h>
9 #include <fdt_support.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/fdt.h>
14 #include <asm/arch/soc.h>
15 #include <ahci.h>
16 #include <hwconfig.h>
17 #include <mmc.h>
18 #include <scsi.h>
19 #include <fm_eth.h>
20 #include <fsl_csu.h>
21 #include <fsl_esdhc.h>
22 #include <fsl_ifc.h>
23 #include <spl.h>
24 
25 #include "../common/qixis.h"
26 #include "ls1043aqds_qixis.h"
27 
28 DECLARE_GLOBAL_DATA_PTR;
29 
30 enum {
31 	MUX_TYPE_GPIO,
32 };
33 
34 /* LS1043AQDS serdes mux */
35 #define CFG_SD_MUX1_SLOT2	0x0 /* SLOT2 TX/RX0 */
36 #define CFG_SD_MUX1_SLOT1	0x1 /* SLOT1 TX/RX1 */
37 #define CFG_SD_MUX2_SLOT3	0x0 /* SLOT3 TX/RX0 */
38 #define CFG_SD_MUX2_SLOT1	0x1 /* SLOT1 TX/RX2 */
39 #define CFG_SD_MUX3_SLOT4	0x0 /* SLOT4 TX/RX0 */
40 #define CFG_SD_MUX3_MUX4	0x1 /* MUX4 */
41 #define CFG_SD_MUX4_SLOT3	0x0 /* SLOT3 TX/RX1 */
42 #define CFG_SD_MUX4_SLOT1	0x1 /* SLOT1 TX/RX3 */
43 #define CFG_UART_MUX_MASK	0x6
44 #define CFG_UART_MUX_SHIFT	1
45 #define CFG_LPUART_EN		0x1
46 
47 int checkboard(void)
48 {
49 	char buf[64];
50 #ifndef CONFIG_SD_BOOT
51 	u8 sw;
52 #endif
53 
54 	puts("Board: LS1043AQDS, boot from ");
55 
56 #ifdef CONFIG_SD_BOOT
57 	puts("SD\n");
58 #else
59 	sw = QIXIS_READ(brdcfg[0]);
60 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
61 
62 	if (sw < 0x8)
63 		printf("vBank: %d\n", sw);
64 	else if (sw == 0x8)
65 		puts("PromJet\n");
66 	else if (sw == 0x9)
67 		puts("NAND\n");
68 	else if (sw == 0xF)
69 		printf("QSPI\n");
70 	else
71 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
72 #endif
73 
74 	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
75 	       QIXIS_READ(id), QIXIS_READ(arch));
76 
77 	printf("FPGA:  v%d (%s), build %d\n",
78 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
79 	       (int)qixis_read_minor());
80 
81 	return 0;
82 }
83 
84 bool if_board_diff_clk(void)
85 {
86 	u8 diff_conf = QIXIS_READ(brdcfg[11]);
87 
88 	return diff_conf & 0x40;
89 }
90 
91 unsigned long get_board_sys_clk(void)
92 {
93 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
94 
95 	switch (sysclk_conf & 0x0f) {
96 	case QIXIS_SYSCLK_64:
97 		return 64000000;
98 	case QIXIS_SYSCLK_83:
99 		return 83333333;
100 	case QIXIS_SYSCLK_100:
101 		return 100000000;
102 	case QIXIS_SYSCLK_125:
103 		return 125000000;
104 	case QIXIS_SYSCLK_133:
105 		return 133333333;
106 	case QIXIS_SYSCLK_150:
107 		return 150000000;
108 	case QIXIS_SYSCLK_160:
109 		return 160000000;
110 	case QIXIS_SYSCLK_166:
111 		return 166666666;
112 	}
113 
114 	return 66666666;
115 }
116 
117 unsigned long get_board_ddr_clk(void)
118 {
119 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
120 
121 	if (if_board_diff_clk())
122 		return get_board_sys_clk();
123 	switch ((ddrclk_conf & 0x30) >> 4) {
124 	case QIXIS_DDRCLK_100:
125 		return 100000000;
126 	case QIXIS_DDRCLK_125:
127 		return 125000000;
128 	case QIXIS_DDRCLK_133:
129 		return 133333333;
130 	}
131 
132 	return 66666666;
133 }
134 
135 int select_i2c_ch_pca9547(u8 ch)
136 {
137 	int ret;
138 
139 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
140 	if (ret) {
141 		puts("PCA: failed to select proper channel\n");
142 		return ret;
143 	}
144 
145 	return 0;
146 }
147 
148 int dram_init(void)
149 {
150 	/*
151 	 * When resuming from deep sleep, the I2C channel may not be
152 	 * in the default channel. So, switch to the default channel
153 	 * before accessing DDR SPD.
154 	 */
155 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
156 	gd->ram_size = initdram(0);
157 
158 	return 0;
159 }
160 
161 int i2c_multiplexer_select_vid_channel(u8 channel)
162 {
163 	return select_i2c_ch_pca9547(channel);
164 }
165 
166 void board_retimer_init(void)
167 {
168 	u8 reg;
169 
170 	/* Retimer is connected to I2C1_CH7_CH5 */
171 	select_i2c_ch_pca9547(I2C_MUX_CH7);
172 	reg = I2C_MUX_CH5;
173 	i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
174 
175 	/* Access to Control/Shared register */
176 	reg = 0x0;
177 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
178 
179 	/* Read device revision and ID */
180 	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
181 	debug("Retimer version id = 0x%x\n", reg);
182 
183 	/* Enable Broadcast. All writes target all channel register sets */
184 	reg = 0x0c;
185 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
186 
187 	/* Reset Channel Registers */
188 	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
189 	reg |= 0x4;
190 	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
191 
192 	/* Enable override divider select and Enable Override Output Mux */
193 	i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
194 	reg |= 0x24;
195 	i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
196 
197 	/* Select VCO Divider to full rate (000) */
198 	i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
199 	reg &= 0x8f;
200 	i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
201 
202 	/* Selects active PFD MUX Input as Re-timed Data (001) */
203 	i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
204 	reg &= 0x3f;
205 	reg |= 0x20;
206 	i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
207 
208 	/* Set data rate as 10.3125 Gbps */
209 	reg = 0x0;
210 	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
211 	reg = 0xb2;
212 	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
213 	reg = 0x90;
214 	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
215 	reg = 0xb3;
216 	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
217 	reg = 0xcd;
218 	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
219 
220 	/* Return the default channel */
221 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
222 }
223 
224 int board_early_init_f(void)
225 {
226 #ifdef CONFIG_HAS_FSL_XHCI_USB
227 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
228 	u32 usb_pwrfault;
229 #endif
230 #ifdef CONFIG_LPUART
231 	u8 uart;
232 #endif
233 
234 #ifdef CONFIG_SYS_I2C_EARLY_INIT
235 	i2c_early_init_f();
236 #endif
237 	fsl_lsch2_early_init_f();
238 
239 #ifdef CONFIG_HAS_FSL_XHCI_USB
240 	out_be32(&scfg->rcwpmuxcr0, 0x3333);
241 	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
242 	usb_pwrfault =
243 		(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
244 		(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
245 		(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
246 	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
247 #endif
248 
249 #ifdef CONFIG_LPUART
250 	/* We use lpuart0 as system console */
251 	uart = QIXIS_READ(brdcfg[14]);
252 	uart &= ~CFG_UART_MUX_MASK;
253 	uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
254 	QIXIS_WRITE(brdcfg[14], uart);
255 #endif
256 
257 	return 0;
258 }
259 
260 #ifdef CONFIG_FSL_DEEP_SLEEP
261 /* determine if it is a warm boot */
262 bool is_warm_boot(void)
263 {
264 #define DCFG_CCSR_CRSTSR_WDRFR	(1 << 3)
265 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
266 
267 	if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
268 		return 1;
269 
270 	return 0;
271 }
272 #endif
273 
274 int config_board_mux(int ctrl_type)
275 {
276 	u8 reg14;
277 
278 	reg14 = QIXIS_READ(brdcfg[14]);
279 
280 	switch (ctrl_type) {
281 	case MUX_TYPE_GPIO:
282 		reg14 = (reg14 & (~0x30)) | 0x20;
283 		break;
284 	default:
285 		puts("Unsupported mux interface type\n");
286 		return -1;
287 	}
288 
289 	QIXIS_WRITE(brdcfg[14], reg14);
290 
291 	return 0;
292 }
293 
294 int config_serdes_mux(void)
295 {
296 	return 0;
297 }
298 
299 
300 #ifdef CONFIG_MISC_INIT_R
301 int misc_init_r(void)
302 {
303 	if (hwconfig("gpio"))
304 		config_board_mux(MUX_TYPE_GPIO);
305 
306 	return 0;
307 }
308 #endif
309 
310 int board_init(void)
311 {
312 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
313 	board_retimer_init();
314 
315 #ifdef CONFIG_SYS_FSL_SERDES
316 	config_serdes_mux();
317 #endif
318 
319 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
320 	enable_layerscape_ns_access();
321 #endif
322 	return 0;
323 }
324 
325 #ifdef CONFIG_OF_BOARD_SETUP
326 int ft_board_setup(void *blob, bd_t *bd)
327 {
328 	u64 base[CONFIG_NR_DRAM_BANKS];
329 	u64 size[CONFIG_NR_DRAM_BANKS];
330 	u8 reg;
331 
332 	/* fixup DT for the two DDR banks */
333 	base[0] = gd->bd->bi_dram[0].start;
334 	size[0] = gd->bd->bi_dram[0].size;
335 	base[1] = gd->bd->bi_dram[1].start;
336 	size[1] = gd->bd->bi_dram[1].size;
337 
338 	fdt_fixup_memory_banks(blob, base, size, 2);
339 	ft_cpu_setup(blob, bd);
340 
341 #ifdef CONFIG_SYS_DPAA_FMAN
342 	fdt_fixup_fman_ethernet(blob);
343 	fdt_fixup_board_enet(blob);
344 #endif
345 
346 	reg = QIXIS_READ(brdcfg[0]);
347 	reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
348 
349 	/* Disable IFC if QSPI is enabled */
350 	if (reg == 0xF)
351 		do_fixup_by_compat(blob, "fsl,ifc",
352 				   "status", "disabled", 8 + 1, 1);
353 
354 	return 0;
355 }
356 #endif
357 
358 u8 flash_read8(void *addr)
359 {
360 	return __raw_readb(addr + 1);
361 }
362 
363 void flash_write16(u16 val, void *addr)
364 {
365 	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
366 
367 	__raw_writew(shftval, addr);
368 }
369 
370 u16 flash_read16(void *addr)
371 {
372 	u16 val = __raw_readw(addr);
373 
374 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
375 }
376