1 /*
2  * Copyright 2015 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <i2c.h>
9 #include <fdt_support.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/fdt.h>
14 #include <asm/arch/soc.h>
15 #include <ahci.h>
16 #include <hwconfig.h>
17 #include <mmc.h>
18 #include <scsi.h>
19 #include <fm_eth.h>
20 #include <fsl_csu.h>
21 #include <fsl_esdhc.h>
22 #include <fsl_ifc.h>
23 #include <spl.h>
24 
25 #include "../common/qixis.h"
26 #include "ls1043aqds_qixis.h"
27 
28 DECLARE_GLOBAL_DATA_PTR;
29 
30 enum {
31 	MUX_TYPE_GPIO,
32 };
33 
34 /* LS1043AQDS serdes mux */
35 #define CFG_SD_MUX1_SLOT2	0x0 /* SLOT2 TX/RX0 */
36 #define CFG_SD_MUX1_SLOT1	0x1 /* SLOT1 TX/RX1 */
37 #define CFG_SD_MUX2_SLOT3	0x0 /* SLOT3 TX/RX0 */
38 #define CFG_SD_MUX2_SLOT1	0x1 /* SLOT1 TX/RX2 */
39 #define CFG_SD_MUX3_SLOT4	0x0 /* SLOT4 TX/RX0 */
40 #define CFG_SD_MUX3_MUX4	0x1 /* MUX4 */
41 #define CFG_SD_MUX4_SLOT3	0x0 /* SLOT3 TX/RX1 */
42 #define CFG_SD_MUX4_SLOT1	0x1 /* SLOT1 TX/RX3 */
43 #define CFG_UART_MUX_MASK	0x6
44 #define CFG_UART_MUX_SHIFT	1
45 #define CFG_LPUART_EN		0x1
46 
47 int checkboard(void)
48 {
49 	char buf[64];
50 #ifndef CONFIG_SD_BOOT
51 	u8 sw;
52 #endif
53 
54 	puts("Board: LS1043AQDS, boot from ");
55 
56 #ifdef CONFIG_SD_BOOT
57 	puts("SD\n");
58 #else
59 	sw = QIXIS_READ(brdcfg[0]);
60 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
61 
62 	if (sw < 0x8)
63 		printf("vBank: %d\n", sw);
64 	else if (sw == 0x8)
65 		puts("PromJet\n");
66 	else if (sw == 0x9)
67 		puts("NAND\n");
68 	else if (sw == 0x15)
69 		printf("IFCCard\n");
70 	else
71 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
72 #endif
73 
74 	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
75 	       QIXIS_READ(id), QIXIS_READ(arch));
76 
77 	printf("FPGA:  v%d (%s), build %d\n",
78 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
79 	       (int)qixis_read_minor());
80 
81 	return 0;
82 }
83 
84 bool if_board_diff_clk(void)
85 {
86 	u8 diff_conf = QIXIS_READ(brdcfg[11]);
87 
88 	return diff_conf & 0x40;
89 }
90 
91 unsigned long get_board_sys_clk(void)
92 {
93 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
94 
95 	switch (sysclk_conf & 0x0f) {
96 	case QIXIS_SYSCLK_64:
97 		return 64000000;
98 	case QIXIS_SYSCLK_83:
99 		return 83333333;
100 	case QIXIS_SYSCLK_100:
101 		return 100000000;
102 	case QIXIS_SYSCLK_125:
103 		return 125000000;
104 	case QIXIS_SYSCLK_133:
105 		return 133333333;
106 	case QIXIS_SYSCLK_150:
107 		return 150000000;
108 	case QIXIS_SYSCLK_160:
109 		return 160000000;
110 	case QIXIS_SYSCLK_166:
111 		return 166666666;
112 	}
113 
114 	return 66666666;
115 }
116 
117 unsigned long get_board_ddr_clk(void)
118 {
119 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
120 
121 	if (if_board_diff_clk())
122 		return get_board_sys_clk();
123 	switch ((ddrclk_conf & 0x30) >> 4) {
124 	case QIXIS_DDRCLK_100:
125 		return 100000000;
126 	case QIXIS_DDRCLK_125:
127 		return 125000000;
128 	case QIXIS_DDRCLK_133:
129 		return 133333333;
130 	}
131 
132 	return 66666666;
133 }
134 
135 int select_i2c_ch_pca9547(u8 ch)
136 {
137 	int ret;
138 
139 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
140 	if (ret) {
141 		puts("PCA: failed to select proper channel\n");
142 		return ret;
143 	}
144 
145 	return 0;
146 }
147 
148 int dram_init(void)
149 {
150 	/*
151 	 * When resuming from deep sleep, the I2C channel may not be
152 	 * in the default channel. So, switch to the default channel
153 	 * before accessing DDR SPD.
154 	 */
155 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
156 	gd->ram_size = initdram(0);
157 
158 	return 0;
159 }
160 
161 int i2c_multiplexer_select_vid_channel(u8 channel)
162 {
163 	return select_i2c_ch_pca9547(channel);
164 }
165 
166 void board_retimer_init(void)
167 {
168 	u8 reg;
169 
170 	/* Retimer is connected to I2C1_CH7_CH5 */
171 	reg = I2C_MUX_CH7;
172 	i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
173 	reg = I2C_MUX_CH5;
174 	i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
175 
176 	/* Access to Control/Shared register */
177 	reg = 0x0;
178 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
179 
180 	/* Read device revision and ID */
181 	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
182 	debug("Retimer version id = 0x%x\n", reg);
183 
184 	/* Enable Broadcast. All writes target all channel register sets */
185 	reg = 0x0c;
186 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
187 
188 	/* Reset Channel Registers */
189 	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
190 	reg |= 0x4;
191 	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
192 
193 	/* Enable override divider select and Enable Override Output Mux */
194 	i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
195 	reg |= 0x24;
196 	i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
197 
198 	/* Select VCO Divider to full rate (000) */
199 	i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
200 	reg &= 0x8f;
201 	i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
202 
203 	/* Selects active PFD MUX Input as Re-timed Data (001) */
204 	i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
205 	reg &= 0x3f;
206 	reg |= 0x20;
207 	i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
208 
209 	/* Set data rate as 10.3125 Gbps */
210 	reg = 0x0;
211 	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
212 	reg = 0xb2;
213 	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
214 	reg = 0x90;
215 	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
216 	reg = 0xb3;
217 	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
218 	reg = 0xcd;
219 	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
220 }
221 
222 int board_early_init_f(void)
223 {
224 #ifdef CONFIG_LPUART
225 	u8 uart;
226 #endif
227 	fsl_lsch2_early_init_f();
228 #ifdef CONFIG_LPUART
229 	/* We use lpuart0 as system console */
230 	uart = QIXIS_READ(brdcfg[14]);
231 	uart &= ~CFG_UART_MUX_MASK;
232 	uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
233 	QIXIS_WRITE(brdcfg[14], uart);
234 #endif
235 
236 	return 0;
237 }
238 
239 #ifdef CONFIG_FSL_DEEP_SLEEP
240 /* determine if it is a warm boot */
241 bool is_warm_boot(void)
242 {
243 #define DCFG_CCSR_CRSTSR_WDRFR	(1 << 3)
244 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
245 
246 	if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
247 		return 1;
248 
249 	return 0;
250 }
251 #endif
252 
253 int config_board_mux(int ctrl_type)
254 {
255 	u8 reg14;
256 
257 	reg14 = QIXIS_READ(brdcfg[14]);
258 
259 	switch (ctrl_type) {
260 	case MUX_TYPE_GPIO:
261 		reg14 = (reg14 & (~0x30)) | 0x20;
262 		break;
263 	default:
264 		puts("Unsupported mux interface type\n");
265 		return -1;
266 	}
267 
268 	QIXIS_WRITE(brdcfg[14], reg14);
269 
270 	return 0;
271 }
272 
273 int config_serdes_mux(void)
274 {
275 	return 0;
276 }
277 
278 
279 #ifdef CONFIG_MISC_INIT_R
280 int misc_init_r(void)
281 {
282 	if (hwconfig("gpio"))
283 		config_board_mux(MUX_TYPE_GPIO);
284 
285 	return 0;
286 }
287 #endif
288 
289 int board_init(void)
290 {
291 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
292 				   CONFIG_SYS_CCI400_ADDR;
293 
294 	/* Set CCI-400 control override register to enable barrier
295 	 * transaction */
296 	out_le32(&cci->ctrl_ord,
297 		 CCI400_CTRLORD_EN_BARRIER);
298 
299 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
300 	board_retimer_init();
301 
302 #ifdef CONFIG_SYS_FSL_SERDES
303 	config_serdes_mux();
304 #endif
305 
306 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
307 	enable_layerscape_ns_access();
308 #endif
309 
310 #ifdef CONFIG_ENV_IS_NOWHERE
311 	gd->env_addr = (ulong)&default_environment[0];
312 #endif
313 	return 0;
314 }
315 
316 #ifdef CONFIG_OF_BOARD_SETUP
317 int ft_board_setup(void *blob, bd_t *bd)
318 {
319 	u64 base[CONFIG_NR_DRAM_BANKS];
320 	u64 size[CONFIG_NR_DRAM_BANKS];
321 
322 	/* fixup DT for the two DDR banks */
323 	base[0] = gd->bd->bi_dram[0].start;
324 	size[0] = gd->bd->bi_dram[0].size;
325 	base[1] = gd->bd->bi_dram[1].start;
326 	size[1] = gd->bd->bi_dram[1].size;
327 
328 	fdt_fixup_memory_banks(blob, base, size, 2);
329 	ft_cpu_setup(blob, bd);
330 
331 #ifdef CONFIG_SYS_DPAA_FMAN
332 	fdt_fixup_fman_ethernet(blob);
333 	fdt_fixup_board_enet(blob);
334 #endif
335 	return 0;
336 }
337 #endif
338 
339 u8 flash_read8(void *addr)
340 {
341 	return __raw_readb(addr + 1);
342 }
343 
344 void flash_write16(u16 val, void *addr)
345 {
346 	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
347 
348 	__raw_writew(shftval, addr);
349 }
350 
351 u16 flash_read16(void *addr)
352 {
353 	u16 val = __raw_readw(addr);
354 
355 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
356 }
357