1 /*
2  * Copyright 2015 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <i2c.h>
9 #include <fdt_support.h>
10 #include <fsl_ddr_sdram.h>
11 #include <asm/io.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/fsl_serdes.h>
14 #include <asm/arch/ppa.h>
15 #include <asm/arch/fdt.h>
16 #include <asm/arch/mmu.h>
17 #include <asm/arch/soc.h>
18 #include <ahci.h>
19 #include <hwconfig.h>
20 #include <mmc.h>
21 #include <scsi.h>
22 #include <fm_eth.h>
23 #include <fsl_esdhc.h>
24 #include <fsl_ifc.h>
25 #include <spl.h>
26 
27 #include "../common/qixis.h"
28 #include "ls1043aqds_qixis.h"
29 
30 DECLARE_GLOBAL_DATA_PTR;
31 
32 enum {
33 	MUX_TYPE_GPIO,
34 };
35 
36 /* LS1043AQDS serdes mux */
37 #define CFG_SD_MUX1_SLOT2	0x0 /* SLOT2 TX/RX0 */
38 #define CFG_SD_MUX1_SLOT1	0x1 /* SLOT1 TX/RX1 */
39 #define CFG_SD_MUX2_SLOT3	0x0 /* SLOT3 TX/RX0 */
40 #define CFG_SD_MUX2_SLOT1	0x1 /* SLOT1 TX/RX2 */
41 #define CFG_SD_MUX3_SLOT4	0x0 /* SLOT4 TX/RX0 */
42 #define CFG_SD_MUX3_MUX4	0x1 /* MUX4 */
43 #define CFG_SD_MUX4_SLOT3	0x0 /* SLOT3 TX/RX1 */
44 #define CFG_SD_MUX4_SLOT1	0x1 /* SLOT1 TX/RX3 */
45 #define CFG_UART_MUX_MASK	0x6
46 #define CFG_UART_MUX_SHIFT	1
47 #define CFG_LPUART_EN		0x1
48 
49 int checkboard(void)
50 {
51 	char buf[64];
52 #ifndef CONFIG_SD_BOOT
53 	u8 sw;
54 #endif
55 
56 	puts("Board: LS1043AQDS, boot from ");
57 
58 #ifdef CONFIG_SD_BOOT
59 	puts("SD\n");
60 #else
61 	sw = QIXIS_READ(brdcfg[0]);
62 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
63 
64 	if (sw < 0x8)
65 		printf("vBank: %d\n", sw);
66 	else if (sw == 0x8)
67 		puts("PromJet\n");
68 	else if (sw == 0x9)
69 		puts("NAND\n");
70 	else if (sw == 0xF)
71 		printf("QSPI\n");
72 	else
73 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
74 #endif
75 
76 	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
77 	       QIXIS_READ(id), QIXIS_READ(arch));
78 
79 	printf("FPGA:  v%d (%s), build %d\n",
80 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
81 	       (int)qixis_read_minor());
82 
83 	return 0;
84 }
85 
86 bool if_board_diff_clk(void)
87 {
88 	u8 diff_conf = QIXIS_READ(brdcfg[11]);
89 
90 	return diff_conf & 0x40;
91 }
92 
93 unsigned long get_board_sys_clk(void)
94 {
95 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
96 
97 	switch (sysclk_conf & 0x0f) {
98 	case QIXIS_SYSCLK_64:
99 		return 64000000;
100 	case QIXIS_SYSCLK_83:
101 		return 83333333;
102 	case QIXIS_SYSCLK_100:
103 		return 100000000;
104 	case QIXIS_SYSCLK_125:
105 		return 125000000;
106 	case QIXIS_SYSCLK_133:
107 		return 133333333;
108 	case QIXIS_SYSCLK_150:
109 		return 150000000;
110 	case QIXIS_SYSCLK_160:
111 		return 160000000;
112 	case QIXIS_SYSCLK_166:
113 		return 166666666;
114 	}
115 
116 	return 66666666;
117 }
118 
119 unsigned long get_board_ddr_clk(void)
120 {
121 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
122 
123 	if (if_board_diff_clk())
124 		return get_board_sys_clk();
125 	switch ((ddrclk_conf & 0x30) >> 4) {
126 	case QIXIS_DDRCLK_100:
127 		return 100000000;
128 	case QIXIS_DDRCLK_125:
129 		return 125000000;
130 	case QIXIS_DDRCLK_133:
131 		return 133333333;
132 	}
133 
134 	return 66666666;
135 }
136 
137 int select_i2c_ch_pca9547(u8 ch)
138 {
139 	int ret;
140 
141 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
142 	if (ret) {
143 		puts("PCA: failed to select proper channel\n");
144 		return ret;
145 	}
146 
147 	return 0;
148 }
149 
150 int dram_init(void)
151 {
152 	/*
153 	 * When resuming from deep sleep, the I2C channel may not be
154 	 * in the default channel. So, switch to the default channel
155 	 * before accessing DDR SPD.
156 	 */
157 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
158 	fsl_initdram();
159 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
160 	/* This will break-before-make MMU for DDR */
161 	update_early_mmu_table();
162 #endif
163 
164 	return 0;
165 }
166 
167 int i2c_multiplexer_select_vid_channel(u8 channel)
168 {
169 	return select_i2c_ch_pca9547(channel);
170 }
171 
172 void board_retimer_init(void)
173 {
174 	u8 reg;
175 
176 	/* Retimer is connected to I2C1_CH7_CH5 */
177 	select_i2c_ch_pca9547(I2C_MUX_CH7);
178 	reg = I2C_MUX_CH5;
179 	i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
180 
181 	/* Access to Control/Shared register */
182 	reg = 0x0;
183 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
184 
185 	/* Read device revision and ID */
186 	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
187 	debug("Retimer version id = 0x%x\n", reg);
188 
189 	/* Enable Broadcast. All writes target all channel register sets */
190 	reg = 0x0c;
191 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
192 
193 	/* Reset Channel Registers */
194 	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
195 	reg |= 0x4;
196 	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
197 
198 	/* Enable override divider select and Enable Override Output Mux */
199 	i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
200 	reg |= 0x24;
201 	i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
202 
203 	/* Select VCO Divider to full rate (000) */
204 	i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
205 	reg &= 0x8f;
206 	i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
207 
208 	/* Selects active PFD MUX Input as Re-timed Data (001) */
209 	i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
210 	reg &= 0x3f;
211 	reg |= 0x20;
212 	i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
213 
214 	/* Set data rate as 10.3125 Gbps */
215 	reg = 0x0;
216 	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
217 	reg = 0xb2;
218 	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
219 	reg = 0x90;
220 	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
221 	reg = 0xb3;
222 	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
223 	reg = 0xcd;
224 	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
225 
226 	/* Return the default channel */
227 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
228 }
229 
230 int board_early_init_f(void)
231 {
232 #ifdef CONFIG_HAS_FSL_XHCI_USB
233 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
234 	u32 usb_pwrfault;
235 #endif
236 #ifdef CONFIG_LPUART
237 	u8 uart;
238 #endif
239 
240 #ifdef CONFIG_SYS_I2C_EARLY_INIT
241 	i2c_early_init_f();
242 #endif
243 	fsl_lsch2_early_init_f();
244 
245 #ifdef CONFIG_HAS_FSL_XHCI_USB
246 	out_be32(&scfg->rcwpmuxcr0, 0x3333);
247 	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
248 	usb_pwrfault =
249 		(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
250 		(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
251 		(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
252 	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
253 #endif
254 
255 #ifdef CONFIG_LPUART
256 	/* We use lpuart0 as system console */
257 	uart = QIXIS_READ(brdcfg[14]);
258 	uart &= ~CFG_UART_MUX_MASK;
259 	uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
260 	QIXIS_WRITE(brdcfg[14], uart);
261 #endif
262 
263 	return 0;
264 }
265 
266 #ifdef CONFIG_FSL_DEEP_SLEEP
267 /* determine if it is a warm boot */
268 bool is_warm_boot(void)
269 {
270 #define DCFG_CCSR_CRSTSR_WDRFR	(1 << 3)
271 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
272 
273 	if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
274 		return 1;
275 
276 	return 0;
277 }
278 #endif
279 
280 int config_board_mux(int ctrl_type)
281 {
282 	u8 reg14;
283 
284 	reg14 = QIXIS_READ(brdcfg[14]);
285 
286 	switch (ctrl_type) {
287 	case MUX_TYPE_GPIO:
288 		reg14 = (reg14 & (~0x30)) | 0x20;
289 		break;
290 	default:
291 		puts("Unsupported mux interface type\n");
292 		return -1;
293 	}
294 
295 	QIXIS_WRITE(brdcfg[14], reg14);
296 
297 	return 0;
298 }
299 
300 int config_serdes_mux(void)
301 {
302 	return 0;
303 }
304 
305 
306 #ifdef CONFIG_MISC_INIT_R
307 int misc_init_r(void)
308 {
309 	if (hwconfig("gpio"))
310 		config_board_mux(MUX_TYPE_GPIO);
311 
312 	return 0;
313 }
314 #endif
315 
316 int board_init(void)
317 {
318 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
319 	erratum_a010315();
320 #endif
321 
322 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
323 	board_retimer_init();
324 
325 #ifdef CONFIG_SYS_FSL_SERDES
326 	config_serdes_mux();
327 #endif
328 
329 #ifdef CONFIG_FSL_LS_PPA
330 	ppa_init();
331 #endif
332 
333 	return 0;
334 }
335 
336 #ifdef CONFIG_OF_BOARD_SETUP
337 int ft_board_setup(void *blob, bd_t *bd)
338 {
339 	u64 base[CONFIG_NR_DRAM_BANKS];
340 	u64 size[CONFIG_NR_DRAM_BANKS];
341 	u8 reg;
342 
343 	/* fixup DT for the two DDR banks */
344 	base[0] = gd->bd->bi_dram[0].start;
345 	size[0] = gd->bd->bi_dram[0].size;
346 	base[1] = gd->bd->bi_dram[1].start;
347 	size[1] = gd->bd->bi_dram[1].size;
348 
349 	fdt_fixup_memory_banks(blob, base, size, 2);
350 	ft_cpu_setup(blob, bd);
351 
352 #ifdef CONFIG_SYS_DPAA_FMAN
353 	fdt_fixup_fman_ethernet(blob);
354 	fdt_fixup_board_enet(blob);
355 #endif
356 
357 	reg = QIXIS_READ(brdcfg[0]);
358 	reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
359 
360 	/* Disable IFC if QSPI is enabled */
361 	if (reg == 0xF)
362 		do_fixup_by_compat(blob, "fsl,ifc",
363 				   "status", "disabled", 8 + 1, 1);
364 
365 	return 0;
366 }
367 #endif
368 
369 u8 flash_read8(void *addr)
370 {
371 	return __raw_readb(addr + 1);
372 }
373 
374 void flash_write16(u16 val, void *addr)
375 {
376 	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
377 
378 	__raw_writew(shftval, addr);
379 }
380 
381 u16 flash_read16(void *addr)
382 {
383 	u16 val = __raw_readw(addr);
384 
385 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
386 }
387