1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <fdt_support.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/fsl_serdes.h> 13 #include <asm/arch/fdt.h> 14 #include <asm/arch/soc.h> 15 #include <ahci.h> 16 #include <hwconfig.h> 17 #include <mmc.h> 18 #include <scsi.h> 19 #include <fm_eth.h> 20 #include <fsl_csu.h> 21 #include <fsl_esdhc.h> 22 #include <fsl_ifc.h> 23 #include <spl.h> 24 25 #include "../common/qixis.h" 26 #include "ls1043aqds_qixis.h" 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 enum { 31 MUX_TYPE_GPIO, 32 }; 33 34 /* LS1043AQDS serdes mux */ 35 #define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */ 36 #define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */ 37 #define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */ 38 #define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */ 39 #define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */ 40 #define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */ 41 #define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */ 42 #define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */ 43 #define CFG_UART_MUX_MASK 0x6 44 #define CFG_UART_MUX_SHIFT 1 45 #define CFG_LPUART_EN 0x1 46 47 int checkboard(void) 48 { 49 char buf[64]; 50 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) 51 u8 sw; 52 #endif 53 54 puts("Board: LS1043AQDS, boot from "); 55 56 #ifdef CONFIG_SD_BOOT 57 puts("SD\n"); 58 #elif defined(CONFIG_QSPI_BOOT) 59 puts("QSPI\n"); 60 #else 61 sw = QIXIS_READ(brdcfg[0]); 62 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 63 64 if (sw < 0x8) 65 printf("vBank: %d\n", sw); 66 else if (sw == 0x8) 67 puts("PromJet\n"); 68 else if (sw == 0x9) 69 puts("NAND\n"); 70 else if (sw == 0x15) 71 printf("IFCCard\n"); 72 else 73 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 74 #endif 75 76 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", 77 QIXIS_READ(id), QIXIS_READ(arch)); 78 79 printf("FPGA: v%d (%s), build %d\n", 80 (int)QIXIS_READ(scver), qixis_read_tag(buf), 81 (int)qixis_read_minor()); 82 83 return 0; 84 } 85 86 bool if_board_diff_clk(void) 87 { 88 u8 diff_conf = QIXIS_READ(brdcfg[11]); 89 90 return diff_conf & 0x40; 91 } 92 93 unsigned long get_board_sys_clk(void) 94 { 95 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 96 97 switch (sysclk_conf & 0x0f) { 98 case QIXIS_SYSCLK_64: 99 return 64000000; 100 case QIXIS_SYSCLK_83: 101 return 83333333; 102 case QIXIS_SYSCLK_100: 103 return 100000000; 104 case QIXIS_SYSCLK_125: 105 return 125000000; 106 case QIXIS_SYSCLK_133: 107 return 133333333; 108 case QIXIS_SYSCLK_150: 109 return 150000000; 110 case QIXIS_SYSCLK_160: 111 return 160000000; 112 case QIXIS_SYSCLK_166: 113 return 166666666; 114 } 115 116 return 66666666; 117 } 118 119 unsigned long get_board_ddr_clk(void) 120 { 121 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 122 123 if (if_board_diff_clk()) 124 return get_board_sys_clk(); 125 switch ((ddrclk_conf & 0x30) >> 4) { 126 case QIXIS_DDRCLK_100: 127 return 100000000; 128 case QIXIS_DDRCLK_125: 129 return 125000000; 130 case QIXIS_DDRCLK_133: 131 return 133333333; 132 } 133 134 return 66666666; 135 } 136 137 int select_i2c_ch_pca9547(u8 ch) 138 { 139 int ret; 140 141 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 142 if (ret) { 143 puts("PCA: failed to select proper channel\n"); 144 return ret; 145 } 146 147 return 0; 148 } 149 150 int dram_init(void) 151 { 152 /* 153 * When resuming from deep sleep, the I2C channel may not be 154 * in the default channel. So, switch to the default channel 155 * before accessing DDR SPD. 156 */ 157 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 158 gd->ram_size = initdram(0); 159 160 return 0; 161 } 162 163 int i2c_multiplexer_select_vid_channel(u8 channel) 164 { 165 return select_i2c_ch_pca9547(channel); 166 } 167 168 void board_retimer_init(void) 169 { 170 u8 reg; 171 172 /* Retimer is connected to I2C1_CH7_CH5 */ 173 reg = I2C_MUX_CH7; 174 i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1); 175 reg = I2C_MUX_CH5; 176 i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); 177 178 /* Access to Control/Shared register */ 179 reg = 0x0; 180 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 181 182 /* Read device revision and ID */ 183 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); 184 debug("Retimer version id = 0x%x\n", reg); 185 186 /* Enable Broadcast. All writes target all channel register sets */ 187 reg = 0x0c; 188 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); 189 190 /* Reset Channel Registers */ 191 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); 192 reg |= 0x4; 193 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); 194 195 /* Enable override divider select and Enable Override Output Mux */ 196 i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1); 197 reg |= 0x24; 198 i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1); 199 200 /* Select VCO Divider to full rate (000) */ 201 i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); 202 reg &= 0x8f; 203 i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); 204 205 /* Selects active PFD MUX Input as Re-timed Data (001) */ 206 i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); 207 reg &= 0x3f; 208 reg |= 0x20; 209 i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); 210 211 /* Set data rate as 10.3125 Gbps */ 212 reg = 0x0; 213 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); 214 reg = 0xb2; 215 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); 216 reg = 0x90; 217 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); 218 reg = 0xb3; 219 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); 220 reg = 0xcd; 221 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); 222 } 223 224 int board_early_init_f(void) 225 { 226 #ifdef CONFIG_HAS_FSL_XHCI_USB 227 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 228 u32 usb_pwrfault; 229 #endif 230 #ifdef CONFIG_LPUART 231 u8 uart; 232 #endif 233 fsl_lsch2_early_init_f(); 234 235 #ifdef CONFIG_HAS_FSL_XHCI_USB 236 out_be32(&scfg->rcwpmuxcr0, 0x3333); 237 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); 238 usb_pwrfault = 239 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB3_SHIFT) | 240 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB2_SHIFT) | 241 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT); 242 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); 243 #endif 244 245 #ifdef CONFIG_LPUART 246 /* We use lpuart0 as system console */ 247 uart = QIXIS_READ(brdcfg[14]); 248 uart &= ~CFG_UART_MUX_MASK; 249 uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; 250 QIXIS_WRITE(brdcfg[14], uart); 251 #endif 252 253 return 0; 254 } 255 256 #ifdef CONFIG_FSL_DEEP_SLEEP 257 /* determine if it is a warm boot */ 258 bool is_warm_boot(void) 259 { 260 #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) 261 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 262 263 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) 264 return 1; 265 266 return 0; 267 } 268 #endif 269 270 int config_board_mux(int ctrl_type) 271 { 272 u8 reg14; 273 274 reg14 = QIXIS_READ(brdcfg[14]); 275 276 switch (ctrl_type) { 277 case MUX_TYPE_GPIO: 278 reg14 = (reg14 & (~0x30)) | 0x20; 279 break; 280 default: 281 puts("Unsupported mux interface type\n"); 282 return -1; 283 } 284 285 QIXIS_WRITE(brdcfg[14], reg14); 286 287 return 0; 288 } 289 290 int config_serdes_mux(void) 291 { 292 return 0; 293 } 294 295 296 #ifdef CONFIG_MISC_INIT_R 297 int misc_init_r(void) 298 { 299 if (hwconfig("gpio")) 300 config_board_mux(MUX_TYPE_GPIO); 301 302 return 0; 303 } 304 #endif 305 306 int board_init(void) 307 { 308 struct ccsr_cci400 *cci = (struct ccsr_cci400 *) 309 CONFIG_SYS_CCI400_ADDR; 310 311 /* Set CCI-400 control override register to enable barrier 312 * transaction */ 313 out_le32(&cci->ctrl_ord, 314 CCI400_CTRLORD_EN_BARRIER); 315 316 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 317 board_retimer_init(); 318 319 #ifdef CONFIG_SYS_FSL_SERDES 320 config_serdes_mux(); 321 #endif 322 323 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 324 enable_layerscape_ns_access(); 325 #endif 326 327 #ifdef CONFIG_ENV_IS_NOWHERE 328 gd->env_addr = (ulong)&default_environment[0]; 329 #endif 330 return 0; 331 } 332 333 #ifdef CONFIG_OF_BOARD_SETUP 334 int ft_board_setup(void *blob, bd_t *bd) 335 { 336 u64 base[CONFIG_NR_DRAM_BANKS]; 337 u64 size[CONFIG_NR_DRAM_BANKS]; 338 339 /* fixup DT for the two DDR banks */ 340 base[0] = gd->bd->bi_dram[0].start; 341 size[0] = gd->bd->bi_dram[0].size; 342 base[1] = gd->bd->bi_dram[1].start; 343 size[1] = gd->bd->bi_dram[1].size; 344 345 fdt_fixup_memory_banks(blob, base, size, 2); 346 ft_cpu_setup(blob, bd); 347 348 #ifdef CONFIG_SYS_DPAA_FMAN 349 fdt_fixup_fman_ethernet(blob); 350 fdt_fixup_board_enet(blob); 351 #endif 352 return 0; 353 } 354 #endif 355 356 u8 flash_read8(void *addr) 357 { 358 return __raw_readb(addr + 1); 359 } 360 361 void flash_write16(u16 val, void *addr) 362 { 363 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 364 365 __raw_writew(shftval, addr); 366 } 367 368 u16 flash_read16(void *addr) 369 { 370 u16 val = __raw_readw(addr); 371 372 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 373 } 374