1 /*
2  * Copyright 2015 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <i2c.h>
9 #include <fdt_support.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/fdt.h>
14 #include <asm/arch/soc.h>
15 #include <ahci.h>
16 #include <hwconfig.h>
17 #include <mmc.h>
18 #include <scsi.h>
19 #include <fm_eth.h>
20 #include <fsl_csu.h>
21 #include <fsl_esdhc.h>
22 #include <fsl_ifc.h>
23 #include <spl.h>
24 
25 #include "../common/qixis.h"
26 #include "ls1043aqds_qixis.h"
27 
28 DECLARE_GLOBAL_DATA_PTR;
29 
30 enum {
31 	MUX_TYPE_GPIO,
32 };
33 
34 /* LS1043AQDS serdes mux */
35 #define CFG_SD_MUX1_SLOT2	0x0 /* SLOT2 TX/RX0 */
36 #define CFG_SD_MUX1_SLOT1	0x1 /* SLOT1 TX/RX1 */
37 #define CFG_SD_MUX2_SLOT3	0x0 /* SLOT3 TX/RX0 */
38 #define CFG_SD_MUX2_SLOT1	0x1 /* SLOT1 TX/RX2 */
39 #define CFG_SD_MUX3_SLOT4	0x0 /* SLOT4 TX/RX0 */
40 #define CFG_SD_MUX3_MUX4	0x1 /* MUX4 */
41 #define CFG_SD_MUX4_SLOT3	0x0 /* SLOT3 TX/RX1 */
42 #define CFG_SD_MUX4_SLOT1	0x1 /* SLOT1 TX/RX3 */
43 
44 int checkboard(void)
45 {
46 	char buf[64];
47 #ifndef CONFIG_SD_BOOT
48 	u8 sw;
49 #endif
50 
51 	puts("Board: LS1043AQDS, boot from ");
52 
53 #ifdef CONFIG_SD_BOOT
54 	puts("SD\n");
55 #else
56 	sw = QIXIS_READ(brdcfg[0]);
57 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
58 
59 	if (sw < 0x8)
60 		printf("vBank: %d\n", sw);
61 	else if (sw == 0x8)
62 		puts("PromJet\n");
63 	else if (sw == 0x9)
64 		puts("NAND\n");
65 	else if (sw == 0x15)
66 		printf("IFCCard\n");
67 	else
68 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
69 #endif
70 
71 	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
72 	       QIXIS_READ(id), QIXIS_READ(arch));
73 
74 	printf("FPGA:  v%d (%s), build %d\n",
75 	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
76 	       (int)qixis_read_minor());
77 
78 	return 0;
79 }
80 
81 bool if_board_diff_clk(void)
82 {
83 	u8 diff_conf = QIXIS_READ(brdcfg[11]);
84 
85 	return diff_conf & 0x40;
86 }
87 
88 unsigned long get_board_sys_clk(void)
89 {
90 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
91 
92 	switch (sysclk_conf & 0x0f) {
93 	case QIXIS_SYSCLK_64:
94 		return 64000000;
95 	case QIXIS_SYSCLK_83:
96 		return 83333333;
97 	case QIXIS_SYSCLK_100:
98 		return 100000000;
99 	case QIXIS_SYSCLK_125:
100 		return 125000000;
101 	case QIXIS_SYSCLK_133:
102 		return 133333333;
103 	case QIXIS_SYSCLK_150:
104 		return 150000000;
105 	case QIXIS_SYSCLK_160:
106 		return 160000000;
107 	case QIXIS_SYSCLK_166:
108 		return 166666666;
109 	}
110 
111 	return 66666666;
112 }
113 
114 unsigned long get_board_ddr_clk(void)
115 {
116 	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
117 
118 	if (if_board_diff_clk())
119 		return get_board_sys_clk();
120 	switch ((ddrclk_conf & 0x30) >> 4) {
121 	case QIXIS_DDRCLK_100:
122 		return 100000000;
123 	case QIXIS_DDRCLK_125:
124 		return 125000000;
125 	case QIXIS_DDRCLK_133:
126 		return 133333333;
127 	}
128 
129 	return 66666666;
130 }
131 
132 int select_i2c_ch_pca9547(u8 ch)
133 {
134 	int ret;
135 
136 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
137 	if (ret) {
138 		puts("PCA: failed to select proper channel\n");
139 		return ret;
140 	}
141 
142 	return 0;
143 }
144 
145 int dram_init(void)
146 {
147 	/*
148 	 * When resuming from deep sleep, the I2C channel may not be
149 	 * in the default channel. So, switch to the default channel
150 	 * before accessing DDR SPD.
151 	 */
152 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
153 	gd->ram_size = initdram(0);
154 
155 	return 0;
156 }
157 
158 int i2c_multiplexer_select_vid_channel(u8 channel)
159 {
160 	return select_i2c_ch_pca9547(channel);
161 }
162 
163 void board_retimer_init(void)
164 {
165 	u8 reg;
166 
167 	/* Retimer is connected to I2C1_CH7_CH5 */
168 	reg = I2C_MUX_CH7;
169 	i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
170 	reg = I2C_MUX_CH5;
171 	i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
172 
173 	/* Access to Control/Shared register */
174 	reg = 0x0;
175 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
176 
177 	/* Read device revision and ID */
178 	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
179 	debug("Retimer version id = 0x%x\n", reg);
180 
181 	/* Enable Broadcast. All writes target all channel register sets */
182 	reg = 0x0c;
183 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
184 
185 	/* Reset Channel Registers */
186 	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
187 	reg |= 0x4;
188 	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
189 
190 	/* Enable override divider select and Enable Override Output Mux */
191 	i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
192 	reg |= 0x24;
193 	i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
194 
195 	/* Select VCO Divider to full rate (000) */
196 	i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
197 	reg &= 0x8f;
198 	i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
199 
200 	/* Selects active PFD MUX Input as Re-timed Data (001) */
201 	i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
202 	reg &= 0x3f;
203 	reg |= 0x20;
204 	i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
205 
206 	/* Set data rate as 10.3125 Gbps */
207 	reg = 0x0;
208 	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
209 	reg = 0xb2;
210 	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
211 	reg = 0x90;
212 	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
213 	reg = 0xb3;
214 	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
215 	reg = 0xcd;
216 	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
217 }
218 
219 int board_early_init_f(void)
220 {
221 	fsl_lsch2_early_init_f();
222 
223 	return 0;
224 }
225 
226 #ifdef CONFIG_FSL_DEEP_SLEEP
227 /* determine if it is a warm boot */
228 bool is_warm_boot(void)
229 {
230 #define DCFG_CCSR_CRSTSR_WDRFR	(1 << 3)
231 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
232 
233 	if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
234 		return 1;
235 
236 	return 0;
237 }
238 #endif
239 
240 int config_board_mux(int ctrl_type)
241 {
242 	u8 reg14;
243 
244 	reg14 = QIXIS_READ(brdcfg[14]);
245 
246 	switch (ctrl_type) {
247 	case MUX_TYPE_GPIO:
248 		reg14 = (reg14 & (~0x30)) | 0x20;
249 		break;
250 	default:
251 		puts("Unsupported mux interface type\n");
252 		return -1;
253 	}
254 
255 	QIXIS_WRITE(brdcfg[14], reg14);
256 
257 	return 0;
258 }
259 
260 int config_serdes_mux(void)
261 {
262 	return 0;
263 }
264 
265 
266 #ifdef CONFIG_MISC_INIT_R
267 int misc_init_r(void)
268 {
269 	if (hwconfig("gpio"))
270 		config_board_mux(MUX_TYPE_GPIO);
271 
272 	return 0;
273 }
274 #endif
275 
276 int board_init(void)
277 {
278 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
279 				   CONFIG_SYS_CCI400_ADDR;
280 
281 	/* Set CCI-400 control override register to enable barrier
282 	 * transaction */
283 	out_le32(&cci->ctrl_ord,
284 		 CCI400_CTRLORD_EN_BARRIER);
285 
286 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
287 	board_retimer_init();
288 
289 #ifdef CONFIG_SYS_FSL_SERDES
290 	config_serdes_mux();
291 #endif
292 
293 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
294 	enable_layerscape_ns_access();
295 #endif
296 
297 #ifdef CONFIG_ENV_IS_NOWHERE
298 	gd->env_addr = (ulong)&default_environment[0];
299 #endif
300 	return 0;
301 }
302 
303 #ifdef CONFIG_OF_BOARD_SETUP
304 int ft_board_setup(void *blob, bd_t *bd)
305 {
306 	ft_cpu_setup(blob, bd);
307 
308 #ifdef CONFIG_SYS_DPAA_FMAN
309 	fdt_fixup_fman_ethernet(blob);
310 	fdt_fixup_board_enet(blob);
311 #endif
312 	return 0;
313 }
314 #endif
315 
316 u8 flash_read8(void *addr)
317 {
318 	return __raw_readb(addr + 1);
319 }
320 
321 void flash_write16(u16 val, void *addr)
322 {
323 	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
324 
325 	__raw_writew(shftval, addr);
326 }
327 
328 u16 flash_read16(void *addr)
329 {
330 	u16 val = __raw_readw(addr);
331 
332 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
333 }
334